diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index d6d059f75..e3ca86837 100755
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
             self.add_sdram("sdram",
                 phy                     = self.sdrphy,
-                module                  = IS42S16160(self.clk_freq, "1:1"),
+                module                  = IS42S16160(sys_clk_freq, "1:1"),
                 origin                  = self.mem_map["main_ram"],
                 size                    = kwargs.get("max_sdram_size", 0x40000000),
                 l2_cache_size           = kwargs.get("l2_size", 8192),
diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 6160dc9fe..a15c9bab9 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -61,7 +61,7 @@ class BaseSoC(SoCCore):
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
-                module                  = MT41J256M16(self.clk_freq, "1:4"),
+                module                  = MT41J256M16(sys_clk_freq, "1:4"),
                 origin                  = self.mem_map["main_ram"],
                 size                    = kwargs.get("max_sdram_size", 0x40000000),
                 l2_cache_size           = kwargs.get("l2_size", 8192),