From 935e4effd20841931fa38f9c7209d72c10d5c631 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 26 Feb 2020 15:13:16 +0100 Subject: [PATCH] interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests) --- litex/soc/interconnect/axi.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 905ef5867..534a0cca2 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -56,7 +56,7 @@ def r_description(data_width, id_width): ] class AXIInterface(Record): - def __init__(self, data_width, address_width, mode="master", id_width=1, clock_domain="sys"): + def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"): self.data_width = data_width self.address_width = address_width self.id_width = id_width