diff --git a/examples/corelogic_conv.py b/examples/corelogic_conv.py
index 9ea4282d5..4bf058ff2 100644
--- a/examples/corelogic_conv.py
+++ b/examples/corelogic_conv.py
@@ -4,5 +4,5 @@ from migen.corelogic import roundrobin, divider
 r = roundrobin.Inst(5)
 d = divider.Inst(16)
 frag = r.get_fragment() + d.get_fragment()
-o = verilog.Convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
+o = verilog.convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
 print(o)
diff --git a/examples/dataflow.py b/examples/dataflow.py
index 31aed2e1a..06c2ab123 100644
--- a/examples/dataflow.py
+++ b/examples/dataflow.py
@@ -3,4 +3,4 @@ from migen.flow.ala import *
 
 act = Divider(32)
 frag = act.get_control_fragment() + act.get_process_fragment()
-print(verilog.Convert(frag))
+print(verilog.convert(frag))
diff --git a/examples/lm32_inst.py b/examples/lm32_inst.py
index 54e75ae23..b4685d520 100644
--- a/examples/lm32_inst.py
+++ b/examples/lm32_inst.py
@@ -44,4 +44,4 @@ cpus = [LM32() for i in range(4)]
 frag = Fragment()
 for cpu in cpus:
 	frag += cpu.get_fragment()
-print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
+print(verilog.convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))
diff --git a/examples/simple_gpio.py b/examples/simple_gpio.py
index da2bd28b3..a6253d394 100644
--- a/examples/simple_gpio.py
+++ b/examples/simple_gpio.py
@@ -21,5 +21,5 @@ bank = csrgen.Bank([oreg, ireg])
 f = bank.get_fragment() + inf
 i = bank.interface
 ofield.dev_r.name = "gpio_out"
-v = verilog.Convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
+v = verilog.convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
 print(v)
diff --git a/examples/wb_intercon/intercon_conv.py b/examples/wb_intercon/intercon_conv.py
index 28cffb28f..11f863cd9 100644
--- a/examples/wb_intercon/intercon_conv.py
+++ b/examples/wb_intercon/intercon_conv.py
@@ -12,7 +12,7 @@ wishbonecon0 = wishbone.InterconnectShared(
 		offset=1)
 
 frag = wishbonecon0.get_fragment()
-v = verilog.Convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
+v = verilog.convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
 	m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
 	s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,
 	s2.cyc_i, s2.stb_i, s2.we_i, s2.adr_i, s2.sel_i, s2.dat_i, s2.dat_o, s2.ack_o})
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index fded97052..15fada6b0 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -182,8 +182,8 @@ def _printinstances(ns, i, clk, rst):
 			r += "\n"
 		r += ");\n\n"
 	return r
-	
-def Convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, ns=None):
+
+def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, ns=None):
 	if clk_signal is None:
 		clk_signal = Signal(name="sys_clk")
 		ios.add(clk_signal)