diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index d6ab38a30..a929a0a8a 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -311,7 +311,7 @@ class Stream2Wishbone(LiteXModule):
 
         # # #
         assert data_width    in [8, 16, 32]
-        assert address_width in [8, 16, 32]
+        assert address_width in [8, 16, 32, 64]
 
         cmd              = Signal(8,                           reset_less=True)
         incr             = Signal()