From 9374196974274aa1ad957afef25578572d2ce81b Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 30 Oct 2023 11:03:16 +0100 Subject: [PATCH] soc/cores/uart: allows 64bits in Stream2Wishbone --- litex/soc/cores/uart.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index d6ab38a30..a929a0a8a 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -311,7 +311,7 @@ class Stream2Wishbone(LiteXModule): # # # assert data_width in [8, 16, 32] - assert address_width in [8, 16, 32] + assert address_width in [8, 16, 32, 64] cmd = Signal(8, reset_less=True) incr = Signal()