From 9416e30249d38a6dd55c25b53ccd9fd72a7469ae Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 4 Oct 2021 14:41:38 +0200
Subject: [PATCH] test/test_icap: Add IPROG sequence check.

---
 litex/soc/cores/icap.py |  5 +++--
 test/test_icap.py       | 29 +++++++++++++++++++++++++----
 2 files changed, 28 insertions(+), 6 deletions(-)

diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py
index 5929f3e16..ad8e12213 100644
--- a/litex/soc/cores/icap.py
+++ b/litex/soc/cores/icap.py
@@ -98,8 +98,9 @@ class ICAP(Module, AutoCSR):
         self.comb += ps_send.i.eq(self.send)
 
         # Generate ICAP bitstream write sequence.
-        self._csib = _csib = Signal(reset=1)
-        self._i    = _i =  Signal(32)
+        self._csib  = _csib  = Signal(reset=1)
+        self._rdwrb = _rdwrb = Signal()
+        self._i     = _i     = Signal(32)
         self.sync.icap += [
             _i.eq(ICAP_DUMMY), # Dummy (Default).
             timeline(ps_send.o, [
diff --git a/test/test_icap.py b/test/test_icap.py
index de8b67373..3a4a961e7 100644
--- a/test/test_icap.py
+++ b/test/test_icap.py
@@ -10,24 +10,45 @@ from migen import *
 
 from litex.soc.cores.icap import *
 
+iprog_sequence = [
+    # csib rdwrb data
+    "0 0 0xaa995566",
+    "0 0 0x20000000",
+    "0 0 0x20000000",
+    "0 0 0x30008001",
+    "0 0 0x0000000f",
+    "0 0 0x20000000",
+    "0 0 0x20000000",
+    "0 0 0x30008001",
+    "0 0 0x0000000d",
+    "0 0 0x20000000",
+    "0 0 0x20000000",
+]
 
 class TestICAP(unittest.TestCase):
     def test_icap_command_reload(self):
         def generator(dut):
             yield dut.addr.eq(ICAPRegisters.CMD)
             yield dut.data.eq(ICAPCMDs.IPROG)
-            for i in range(16):
+            for i in range(8):
                 yield
             yield dut.send.eq(1)
             yield
             yield dut.send.eq(0)
-            for i in range(32):
-                print(f"{(yield dut._i):08x}")
+
+        def check(dut):
+            while (yield dut._i) != ICAP_SYNC:
                 yield
+            for ref_w in iprog_sequence:
+                cur_w = f"{(yield dut._csib)} {(yield dut._rdwrb)} 0x{(yield dut._i):08x}"
+                self.assertEqual(ref_w, cur_w)
+                # print(cur_w)
+                yield
+
 
         dut = ICAP(with_csr=False, simulation=True)
         clocks = {"sys": 10, "icap": 10}
-        run_simulation(dut, generator(dut), clocks, vcd_name="icap.vcd")
+        run_simulation(dut, [generator(dut), check(dut)], clocks, vcd_name="icap.vcd")
 
     def test_icap_bitstream_syntax(self):
         dut = ICAPBitstream(simulation=True)