From 9445c33e9d9e2459c7bf80f826dd7f98a9f0043b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 7 Feb 2020 15:57:46 +0100
Subject: [PATCH] soc: add add_ram/add_rom methods

---
 litex/soc/integration/soc.py      | 32 ++++++++++++++++++++++++++-----
 litex/soc/integration/soc_core.py |  7 +++----
 2 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 0d5506625..59b321a3f 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -38,11 +38,12 @@ def buildtime(with_time=True):
 # SoCRegion ----------------------------------------------------------------------------------------
 
 class SoCRegion:
-    def __init__(self, origin=None, size=None, cached=True):
-        self.logger = logging.getLogger("SoCRegion")
-        self.origin = origin
-        self.size   = size
-        self.cached = cached
+    def __init__(self, origin=None, size=None, cached=True, read_only=False):
+        self.logger    = logging.getLogger("SoCRegion")
+        self.origin    = origin
+        self.size      = size
+        self.cached    = cached
+        self.read_only = read_only
 
     def decoder(self):
         origin = self.origin
@@ -64,6 +65,8 @@ class SoCRegion:
         if self.size is not None:
             r += "Size: {}, ".format(colorer("0x{:08x}".format(self.size)))
         r += "Cached: {}".format(colorer(self.cached))
+        if self.read_only:
+            r += ", Read Only"
         return r
 
 
@@ -534,6 +537,25 @@ class SoC(Module):
         self.logger.info(self.irq)
         self.logger.info(colorer("-"*80, color="bright"))
 
+
+    # SoC main components --------------------------------------------------------------------------
+    def add_ram(self, name, origin, size, contents=[], read_only=False):
+        ram_bus = wishbone.Interface(data_width=self.bus.data_width)
+        ram     = wishbone.SRAM(size, bus=ram_bus, init=contents, read_only=read_only)
+        self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, read_only=read_only))
+        if hasattr(self, name):
+            self.logger.error("{} name already used.".format(colorer(name, "red")))
+            raise
+        self.logger.info("RAM {} {} {}.".format(
+            colorer(name),
+            colorer("added", "green"),
+            self.bus.regions[name]))
+        setattr(self.submodules, name, ram)
+
+    def add_rom(self, name, origin, size, contents=[]):
+        self.add_ram(name, origin, size, contents, read_only=True)
+
+    # SoC finalization -----------------------------------------------------------------------------
     def do_finalize(self):
         self.logger.info(colorer("-"*80, color="bright"))
         self.logger.info(colorer("Finalized SoC:", color="cyan"))
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 5340e8f23..cc2fd0ddf 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -124,6 +124,7 @@ class SoCCore(SoC):
         self.csr_data_width             = csr_data_width
         self.csr_address_width          = csr_address_width
 
+        self.with_wishbone              = with_wishbone
         self.wishbone_timeout_cycles    = wishbone_timeout_cycles
 
         # Modules instances ------------------------------------------------------------------------
@@ -192,13 +193,11 @@ class SoCCore(SoC):
 
         # Add integrated SRAM
         if integrated_sram_size:
-            self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
-            self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
+            self.add_ram("sram", self.soc_mem_map["sram"], integrated_sram_size)
 
         # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
         if integrated_main_ram_size:
-            self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
-            self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
+            self.add_ram("main_ram", self.soc_mem_map["main_ram"], integrated_main_ram_size)
 
         # Add UART
         if with_uart: