From 944732aa1942f563e765e20427c9b228e4345ed7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Sep 2021 15:46:19 +0200 Subject: [PATCH] soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone. --- litex/soc/integration/soc.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index cc8173522..53f8194d8 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1333,12 +1333,10 @@ class LiteXSoC(SoC): mem_wb = wishbone.Interface( data_width = self.cpu.mem_axi.data_width, adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8)) - # FIXME: AXI2Wishbone FSMs must be reset with the CPU. - mem_a2w = ResetInserter()(axi.AXI2Wishbone( + mem_a2w = axi.AXI2Wishbone( axi = self.cpu.mem_axi, wishbone = mem_wb, - base_address = 0)) - self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset) + base_address = 0) self.submodules += mem_a2w litedram_wb = wishbone.Interface(port.data_width) self.submodules += LiteDRAMWishbone2Native(