From 9449bbea0a98a4037d9b84d2878e44a7cc728964 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 21 May 2012 19:56:23 +0200 Subject: [PATCH] Add LICENSE file --- LICENSE | 44 ++++++++++++++++++++++++++++++++++++ README | 46 +------------------------------------- migen/bank/eventmanager.py | 10 ++++----- 3 files changed, 50 insertions(+), 50 deletions(-) create mode 100644 LICENSE diff --git a/LICENSE b/LICENSE new file mode 100644 index 000000000..383bb89c9 --- /dev/null +++ b/LICENSE @@ -0,0 +1,44 @@ +Migen is free software: you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation, version 3 of the License. This program is +distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. + +Additional permissions under section 7 of the GNU General Public License +(GPL) are hereby granted. The purpose of this exception is to allow +non-GPL (including proprietary) logic cores to be used in conjunction +with code generated by Migen in a design. + +"Generated" code refers to Verilog or VHDL code that has been obtained +by converting FHDL structures using Migen. + +To "instantiate" is to include and connect another module as specified +in section 12.1.2 of the IEEE standard 1364-2001 or in section 9.6 of +the IEEE standard 1076-1993. + +(1) You have permission to propagate a work of generated code that + instantiates modules that are not generated code and do not comply + with the GPL. +(2) You have permission to propagate a work of Verilog or VHDL code that + is not generated code, does not comply with the GPL and instantiates + generated code. + +The availability of this exception does not imply any general +presumption that third-party software is unaffected by the copyleft +requirements of the license of Migen. + +Unless otherwise noted, Migen's source code is copyright (C) 2011-2012 +Sebastien Bourdeauducq. + +The simulation extension (as mentioned in the comments at the beginning +of the corresponding source files) is copyright (C) 2012 Vermeer +Manufacturing Co. + +Other authors retain ownership of their contributions. If a submission +can reasonably be considered independently copyrightable, it's yours and +I encourage you to claim it with appropriate copyright notices. This +submission then falls under the "otherwise noted" category. All +submissions must use a license compatible with the GPL and the exception +above. diff --git a/README b/README index 0046db955..45c8e7d8b 100644 --- a/README +++ b/README @@ -22,50 +22,6 @@ Migen is designed for Python 3.2. Send questions, comments and patches to devel [AT] lists.milkymist.org We are also on IRC: #milkymist on the Freenode network. -Migen is free software: you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation, version 3 of the License. This program is -distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. - -Additional permissions under section 7 of the GNU General Public License -(GPL) are hereby granted. The purpose of this exception is to allow -non-GPL (including proprietary) logic cores to be used in conjunction -with code generated by Migen in a design. - -"Generated" code refers to Verilog or VHDL code that has been obtained -by converting FHDL structures using Migen. - -To "instantiate" is to include and connect another module as specified -in section 12.1.2 of the IEEE standard 1364-2001 or in section 9.6 of -the IEEE standard 1076-1993. - -(1) You have permission to propagate a work of generated code that - instantiates modules that are not generated code and do not comply - with the GPL. -(2) You have permission to propagate a work of Verilog or VHDL code that - is not generated code, does not comply with the GPL and instantiates - generated code. - -The availability of this exception does not imply any general -presumption that third-party software is unaffected by the copyleft -requirements of the license of Migen. - -Unless otherwise noted, Migen's source code is copyright (C) 2011-2012 -Sebastien Bourdeauducq. - -The simulation extension (as mentioned in the comments at the beginning -of the corresponding source files) is copyright (C) 2012 Vermeer -Manufacturing Co. - -Other authors retain ownership of their contributions. If a submission -can reasonably be considered independently copyrightable, it's yours and -I encourage you to claim it with appropriate copyright notices. This -submission then falls under the "otherwise noted" category. All -submissions must use a license compatible with the GPL and the exception -above. - +See LICENSE file for copyright and license info. "Electricity! It's like magic!" diff --git a/migen/bank/eventmanager.py b/migen/bank/eventmanager.py index 37a83b2c4..298ec44ab 100644 --- a/migen/bank/eventmanager.py +++ b/migen/bank/eventmanager.py @@ -5,6 +5,7 @@ from migen.corelogic.misc import optree class EventSource: def __init__(self): self.trigger = Signal() + self.pending = Signal() class EventSourcePulse(EventSource): pass @@ -40,22 +41,21 @@ class EventManager: # pending for i, source in enumerate(self.sources): - pending = Signal() # W1C - sync.append(If(self.pending.re & self.pending.r[i], pending.eq(0))) + sync.append(If(self.pending.re & self.pending.r[i], source.pending.eq(0))) if isinstance(source, EventSourcePulse): # set on a positive trigger pulse - sync.append(If(source.trigger, pending.eq(1))) + sync.append(If(source.trigger, source.pending.eq(1))) elif isinstance(source, EventSourceLevel): # set on the falling edge of the trigger old_trigger = Signal() sync += [ old_trigger.eq(source.trigger), - If(~source.trigger & old_trigger, pending.eq(1)) + If(~source.trigger & old_trigger, source.pending.eq(1)) ] else: raise TypeError - comb.append(self.pending.w[i].eq(pending)) + comb.append(self.pending.w[i].eq(source.pending)) # IRQ irqs = [self.pending.w[i] & field.r for i, field in enumerate(self.enable.fields)]