From 948527b0fe8e4bfee8b5010dd8dc119655db2758 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Oct 2018 12:20:32 +0200 Subject: [PATCH] cores/cpu: revert vexriscv (it seems there is a regression in last version) --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- litex/soc/software/include/base/csr-defs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index e8a30b95b..395c5ee28 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit e8a30b95b9aa1445b5a4a76579a98a0552e2db53 +Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5 diff --git a/litex/soc/software/include/base/csr-defs.h b/litex/soc/software/include/base/csr-defs.h index d98e8dfb7..5f5ea8476 100644 --- a/litex/soc/software/include/base/csr-defs.h +++ b/litex/soc/software/include/base/csr-defs.h @@ -3,8 +3,8 @@ #define CSR_MSTATUS_MIE 0x8 -#define CSR_IRQ_MASK 0xBC0 -#define CSR_IRQ_PENDING 0xFC0 +#define CSR_IRQ_MASK 0x330 +#define CSR_IRQ_PENDING 0x360 #define CSR_DCACHE_INFO 0xCC0