From 949a8e73c29ce6575ba8d445c7c6238d8e0a7af4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Jul 2020 08:35:54 +0200 Subject: [PATCH] boards/platforms/versa_ecp5: fix mising update. --- litex/boards/platforms/versa_ecp5.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index 4ea3df466..4ab238307 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -221,8 +221,9 @@ class Platform(LatticePlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs) + def __init__(self, device="LFE5UM5G", **kwargs): + assert device in ["LFE5UM5G", "LFE5UM"] + LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs) def create_programmer(self): return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")