From 94a0a5b0d8968fb52cd193683693bb84676d815a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 19 Jun 2023 09:54:10 +0200
Subject: [PATCH] soc/add_pcie: Add msi_width parameter to select MSI width.

---
 CHANGES.md                   |  1 +
 litex/soc/integration/soc.py | 10 +++++-----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/CHANGES.md b/CHANGES.md
index b708359e5..89de3bde8 100644
--- a/CHANGES.md
+++ b/CHANGES.md
@@ -30,6 +30,7 @@
 	- litex_boards                 : Added QMtech XC7K325T, VCU128, SITLINV_STVL7325_V2, Enclustra XU8/PE3 support.
 	- liteeth                      : Added Ultrascale+ GTY/GTH SGMII/1000BaseX PHYs.
 	- soc/add_pcie                 : Added msi_type parameter to select MSI, MSI-Multi-Vector or MSI-X.
+	- soc/add_pcie                 : Added msi_width parameter to select MSI width.
 
 	[> Changed
 	----------
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index b33edf8b8..bd16393ef 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1971,12 +1971,12 @@ class LiteXSoC(SoC):
 
     # Add PCIe -------------------------------------------------------------------------------------
     def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32,
-        with_dma_buffering = True, dma_buffering_depth=1024,
+        with_dma_buffering    = True, dma_buffering_depth=1024,
         with_dma_loopback     = True,
         with_dma_synchronizer = False,
         with_dma_monitor      = False,
         with_dma_status       = False,
-        with_msi              = True, msi_type="msi",
+        with_msi              = True, msi_type="msi", msi_width=32,
 ):
         # Imports
         from litepcie.phy.uspciephy import USPCIEPHY
@@ -2008,11 +2008,11 @@ class LiteXSoC(SoC):
             assert msi_type in ["msi", "msi-multi-vector", "msi-x"]
             self.check_if_exists(f"{name}_msi")
             if msi_type == "msi":
-                msi = LitePCIeMSI()
+                msi = LitePCIeMSI(width=msi_width)
             if msi_type == "msi-multi-vector":
-                msi = LitePCIeMSIMultiVector()
+                msi = LitePCIeMSIMultiVector(width=msi_width)
             if msi_type == "msi-x":
-                msi = LitePCIeMSIX(endpoint=self.pcie_endpoint)
+                msi = LitePCIeMSIX(endpoint=self.pcie_endpoint, width=msi_width)
             self.add_module(name=f"{name}_msi", module=msi)
             # FIXME: On Ultrascale/Ultrascale+ limit rate of IRQs to 1MHz (to prevent issue with
             # IRQs stalled).