From 94eca8628c95e6ce3dd007b315d13f1574649962 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 12 Dec 2023 15:19:16 +0100 Subject: [PATCH] Revert "soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width" This reverts commit 6d34b8ed87101f52880e020219a3eb0194413955. --- litex/soc/integration/soc.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index b6ac59123..91b3b0931 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1710,12 +1710,15 @@ class LiteXSoC(SoC): if l2_cache_full_memory_we: l2_cache = FullMemoryWE()(l2_cache) self.l2_cache = l2_cache - wb_sdram = self.l2_cache.slave + litedram_wb = self.l2_cache.slave self.add_config("L2_SIZE", l2_cache_size) + else: + litedram_wb = wishbone.Interface(data_width=port.data_width, address_width=32, addressing="word") + self.submodules += wishbone.Converter(wb_sdram, litedram_wb) # Wishbone Slave <--> LiteDRAM bridge. self.wishbone_bridge = LiteDRAMWishbone2Native( - wishbone = wb_sdram, + wishbone = litedram_wb, port = port, base_address = self.bus.regions["main_ram"].origin )