From dcf55ad4f32664eb9edfc5d9f8f03e1778ef4713 Mon Sep 17 00:00:00 2001 From: chmousset Date: Fri, 12 Jul 2019 16:37:23 +0200 Subject: [PATCH] [fix] Slave interface HP0 clk name --- litex/soc/integration/soc_zynq.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py index a5451b251..4758cccbb 100644 --- a/litex/soc/integration/soc_zynq.py +++ b/litex/soc/integration/soc_zynq.py @@ -142,7 +142,7 @@ class SoCZynq(SoCCore): self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout()) self.ps7_params.update( # axi hp0 clk - i_M_AXI_HP0_ACLK=ClockSignal("sys"), + i_S_AXI_HP0_ACLK=ClockSignal("sys"), # axi hp0 aw i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,