From 95bed6de5c51b3caac47f647d7b720c5d7ea78cf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Sep 2022 16:12:52 +0200 Subject: [PATCH] interconnect/wishbone: Allow passing address_width (In byte addressing). This is useful to abstract interfaces and propagate address_width. Idealy, Wishbone should be fully switch to byte addressing since word addressing has been a source of common issues/errors in the past but compatibility issues would need to be evaluated first. --- litex/soc/interconnect/wishbone.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index ba69e4978..d97a3bd66 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -46,9 +46,12 @@ CTI_BURST_END = 0b111 class Interface(Record): - def __init__(self, data_width=32, adr_width=30, bursting=False): + def __init__(self, data_width=32, adr_width=30, bursting=False, **kwargs): self.data_width = data_width - self.adr_width = adr_width + if kwargs.get("address_width", False): + # FIXME: Improve or switch Wishbone to byte addressing instead of word addressing. + adr_width = kwargs["address_width"] - int(log2(data_width//8)) + self.adr_width = adr_width self.bursting = bursting Record.__init__(self, set_layout_parameters(_layout, adr_width = adr_width,