From 95cfa6a82c84ca156868f06c1e24886e8315c777 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 26 Jan 2020 14:29:32 +0100 Subject: [PATCH] platforms/netv2: add pcie pins --- litex/boards/platforms/netv2.py | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/litex/boards/platforms/netv2.py b/litex/boards/platforms/netv2.py index 6948f5e56..2670fd0f2 100644 --- a/litex/boards/platforms/netv2.py +++ b/litex/boards/platforms/netv2.py @@ -71,6 +71,37 @@ _io = [ Misc("SLEW=FAST"), ), + # pcie + ("pcie_x1", 0, + Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("F10")), + Subsignal("clk_n", Pins("E10")), + Subsignal("rx_p", Pins("D11")), + Subsignal("rx_n", Pins("C11")), + Subsignal("tx_p", Pins("D5")), + Subsignal("tx_n", Pins("C5")) + ), + + ("pcie_x2", 0, + Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("F10")), + Subsignal("clk_n", Pins("E10")), + Subsignal("rx_p", Pins("D11 B10")), + Subsignal("rx_n", Pins("C11 A10")), + Subsignal("tx_p", Pins("D5 B6")), + Subsignal("tx_n", Pins("C5 A6")) + ), + + ("pcie_x4", 0, + Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("F10")), + Subsignal("clk_n", Pins("E10")), + Subsignal("rx_p", Pins("D11 B10 D9 B8")), + Subsignal("rx_n", Pins("C11 A10 C9 A8")), + Subsignal("tx_p", Pins("D5 B6 D7 B4")), + Subsignal("tx_n", Pins("C5 A6 C7 A4")) + ), + # ethernet ("eth_clocks", 0, Subsignal("ref_clk", Pins("D17")),