From 9624cce188f72cdbd17315fbdc15264fdd5ef0b8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 Mar 2021 14:25:41 +0100 Subject: [PATCH] cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators. --- litex/soc/cores/video.py | 49 ++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py index 8ccaf0935..b12c0bf9e 100644 --- a/litex/soc/cores/video.py +++ b/litex/soc/cores/video.py @@ -618,6 +618,33 @@ class VideoFrameBuffer(Module, AutoCSR): # Video PHYs --------------------------------------------------------------------------------------- +class Open(Signal): pass + +# VGA (Generic). + +class VideoVGAPHY(Module): + def __init__(self, pads, clock_domain="sys"): + self.sink = sink = stream.Endpoint(video_data_layout) + + # # # + + # Always ack Sink, no backpressure. + self.comb += sink.ready.eq(1) + + # Drive VGA Conrols. + self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain)) + self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain)) + + # Drive VGA Datas. + cbits = len(pads.r) + cshift = (8 - cbits) + for i in range(cbits): + self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain)) + self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain)) + self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain)) + +# DVI (Generic). + class VideoDVIPHY(Module): def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True): self.sink = sink = stream.Endpoint(video_data_layout) @@ -645,25 +672,3 @@ class VideoDVIPHY(Module): self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain)) self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain)) - - -class VideoVGAPHY(Module): - def __init__(self, pads, clock_domain="sys"): - self.sink = sink = stream.Endpoint(video_data_layout) - - # # # - - # Always ack Sink, no backpressure. - self.comb += sink.ready.eq(1) - - # Drive VGA Conrols. - self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain)) - self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain)) - - # Drive VGA Datas. - cbits = len(pads.r) - cshift = (8 - cbits) - for i in range(cbits): - self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain)) - self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain)) - self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))