From 96527b5a3afcad7c48655755a04baa081ed4e789 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 30 Nov 2018 23:12:30 +0100 Subject: [PATCH] soc/interconnect/stream/gearbox: remove bit reversing by changing words order --- litex/soc/interconnect/stream.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 6c47841c0..1bf81ef13 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -404,12 +404,12 @@ class Gearbox(Module): i_cases = {} for i in range(io_lcm//i_dw): - i_cases[i] = shift_register[i_dw*i:i_dw*(i+1)].eq(sink.data[::-1]) + i_cases[i] = shift_register[io_lcm - i_dw*(i+1):io_lcm - i_dw*i].eq(sink.data) self.sync += If(sink.valid & sink.ready, Case(i_count, i_cases)) o_cases = {} for i in range(io_lcm//o_dw): - o_cases[i] = source.data.eq(shift_register[o_dw*i:o_dw*(i+1)][::-1]) + o_cases[i] = source.data.eq(shift_register[io_lcm - o_dw*(i+1):io_lcm - o_dw*i]) self.comb += Case(o_count, o_cases) # TODO: clean up code below