From 9654b40864005d178926462e5f2b380da98a3c13 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 8 Apr 2024 16:45:15 +0200 Subject: [PATCH] Got litex dma to work with vexii --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 7a968b480..bbbbbfa04 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -217,7 +217,7 @@ class VexiiRiscv(CPU): ) if VexiiRiscv.with_dma: - self.dma_bus = dma_bus = axi.AXIInterface(data_width=VexiiRiscv.perf_bus_width, address_width=32, id_width=4) + self.dma_bus = dma_bus = axi.AXIInterface(data_width=VexiiRiscv.internal_bus_width, address_width=32, id_width=4) self.cpu_params.update( # DMA Bus.