From 9814001c797ba319d9c7f748d84e933ea2fa41d6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Feb 2015 10:51:03 +0100 Subject: [PATCH] create cpu dir and move lm32/mor1kx in it --- misoclib/cpu/__init__.py | 0 misoclib/{ => cpu}/lm32/__init__.py | 0 misoclib/{ => cpu}/mor1kx/__init__.py | 0 misoclib/gensoc/__init__.py | 3 ++- 4 files changed, 2 insertions(+), 1 deletion(-) create mode 100644 misoclib/cpu/__init__.py rename misoclib/{ => cpu}/lm32/__init__.py (100%) rename misoclib/{ => cpu}/mor1kx/__init__.py (100%) diff --git a/misoclib/cpu/__init__.py b/misoclib/cpu/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/misoclib/lm32/__init__.py b/misoclib/cpu/lm32/__init__.py similarity index 100% rename from misoclib/lm32/__init__.py rename to misoclib/cpu/lm32/__init__.py diff --git a/misoclib/mor1kx/__init__.py b/misoclib/cpu/mor1kx/__init__.py similarity index 100% rename from misoclib/mor1kx/__init__.py rename to misoclib/cpu/mor1kx/__init__.py diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 1e99d20a4..0db10b2e9 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -6,7 +6,8 @@ from migen.bank import csrgen from migen.bus import wishbone, csr, lasmibus, dfi from migen.bus import wishbone2lasmi, wishbone2csr -from misoclib import lm32, mor1kx, uart, identifier, timer +from misoclib import uart, identifier, timer +from misoclib.cpu import lm32, mor1kx from misoclib.sdram import lasmicon from misoclib.sdram import dfii from misoclib.sdram import memtest