From 98676162a3e240a809af61de55d81fb4156a2f74 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 18 Jun 2021 10:19:27 +0200
Subject: [PATCH] VexRiscv-SMP: Review/Cleanup #906.

---
 litex/soc/cores/cpu/vexriscv_smp/core.py | 12 +++++-----
 litex/tools/litex_json2dts.py            | 29 +++++++++++++++++-------
 2 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index bdc7476cd..f7c837121 100644
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -109,9 +109,9 @@ class VexRiscvSMP(CPU):
         if(args.cpu_per_fpu):
             VexRiscvSMP.cpu_per_fpu = args.cpu_per_fpu
         if(args.with_rvc):
-            VexRiscvSMP.with_rvc     = True
-        if(args.dtlb_size):                    VexRiscvSMP.dtlb_size             = int(args.dtlb_size)
-        if(args.itlb_size):                    VexRiscvSMP.itlb_size             = int(args.itlb_size)
+            VexRiscvSMP.with_rvc = True
+        if(args.dtlb_size): VexRiscvSMP.dtlb_size = int(args.dtlb_size)
+        if(args.itlb_size): VexRiscvSMP.itlb_size = int(args.itlb_size)
 
     # ABI.
     @staticmethod
@@ -372,7 +372,7 @@ class VexRiscvSMP(CPU):
         # Define number of CPUs
         soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
         soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())
-        # constants for cache so we can add them in the DTS
+        # Constants for cache so we can add them in the DTS.
         if (VexRiscvSMP.dcache_size > 0):
             soc.add_constant("cpu_dcache_size", VexRiscvSMP.dcache_size)
             soc.add_constant("cpu_dcache_ways", VexRiscvSMP.dcache_ways)
@@ -381,8 +381,8 @@ class VexRiscvSMP(CPU):
             soc.add_constant("cpu_icache_size", VexRiscvSMP.icache_size)
             soc.add_constant("cpu_icache_ways", VexRiscvSMP.icache_ways)
             soc.add_constant("cpu_icache_block_size", 64) # hardwired?
-        # constants for TLB so we can add them in the DTS
-        # full associative so only the size is described
+        # Constants for TLB so we can add them in the DTS
+        # full associative so only the size is described.
         if (VexRiscvSMP.dtlb_size > 0):
             soc.add_constant("cpu_dtlb_size", VexRiscvSMP.dtlb_size)
             soc.add_constant("cpu_dtlb_ways", VexRiscvSMP.dtlb_size)
diff --git a/litex/tools/litex_json2dts.py b/litex/tools/litex_json2dts.py
index 72c1e60d7..b5d658f43 100755
--- a/litex/tools/litex_json2dts.py
+++ b/litex/tools/litex_json2dts.py
@@ -60,38 +60,50 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
     # CPU ------------------------------------------------------------------------------------------
 
     # VexRiscv-SMP
+    # ------------
     if cpu_name == "vexriscv smp-linux":
-        # cache description
+        # Cache description.
         cache_desc = ""
         if "cpu_dcache_size" in d["constants"]:
             cache_desc += """
                 d-cache-size = <{d_cache_size}>;
                 d-cache-sets = <{d_cache_ways}>;
                 d-cache-block-size = <{d_cache_block_size}>;
-""".format(d_cache_size=d["constants"]["cpu_dcache_size"], d_cache_ways=d["constants"]["cpu_dcache_ways"], d_cache_block_size=d["constants"]["cpu_dcache_block_size"])
+""".format(
+    d_cache_size       = d["constants"]["cpu_dcache_size"],
+    d_cache_ways       = d["constants"]["cpu_dcache_ways"],
+    d_cache_block_size = d["constants"]["cpu_dcache_block_size"])
         if "cpu_icache_size" in d["constants"]:
             cache_desc += """
                 i-cache-size = <{i_cache_size}>;
                 i-cache-sets = <{i_cache_ways}>;
                 i-cache-block-size = <{i_cache_block_size}>;
-""".format(i_cache_size=d["constants"]["cpu_icache_size"], i_cache_ways=d["constants"]["cpu_icache_ways"], i_cache_block_size=d["constants"]["cpu_icache_block_size"])
+""".format(
+    i_cache_size       = d["constants"]["cpu_icache_size"],
+    i_cache_ways       = d["constants"]["cpu_icache_ways"],
+    i_cache_block_size = d["constants"]["cpu_icache_block_size"])
 
-        # tlb description
+        # TLB description.
         tlb_desc = ""
         if "cpu_dtlb_size" in d["constants"]:
             tlb_desc += """
                 d-tlb-size = <{d_tlb_size}>;
                 d-tlb-sets = <{d_tlb_ways}>;
-""".format(d_tlb_size=d["constants"]["cpu_dtlb_size"], d_tlb_ways=d["constants"]["cpu_dtlb_ways"])
+""".format(
+    d_tlb_size = d["constants"]["cpu_dtlb_size"],
+    d_tlb_ways = d["constants"]["cpu_dtlb_ways"])
         if "cpu_itlb_size" in d["constants"]:
             tlb_desc += """
                 i-tlb-size = <{i_tlb_size}>;
                 i-tlb-sets = <{i_tlb_ways}>;
-""".format(i_tlb_size=d["constants"]["cpu_itlb_size"], i_tlb_ways=d["constants"]["cpu_itlb_ways"])
+""".format(
+    i_tlb_size = d["constants"]["cpu_itlb_size"],
+    i_tlb_ways = d["constants"]["cpu_itlb_ways"])
 
+        # CPU(s) Count.
         cpus = range(int(d["constants"]["config_cpu_count"]))
 
-        # topology
+        # CPU(s) Topology.
         cpu_map = ""
         if int(d["constants"]["config_cpu_count"]) > 1:
             cpu_map += """
@@ -136,7 +148,8 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
         }};
 """.format(cpu_map=cpu_map)
 
-    # mor1kx
+    # Mor1kx
+    # ------
     elif cpu_name == "mor1kx":
         dts += """
         cpus {{