From eb1afbad472d864106617750c551f9fbe7db064e Mon Sep 17 00:00:00 2001
From: riktw <rik@justanotherelectronicsblog.com>
Date: Tue, 11 Jul 2023 16:16:51 +0200
Subject: [PATCH] Currently using a lite or minimal Vexriscv config with debug
 and breakpoints throws an error. Updated the GCC_FLAGS to include these two
 variants as well.

---
 litex/soc/cores/cpu/vexriscv/core.py | 50 +++++++++++++++-------------
 1 file changed, 26 insertions(+), 24 deletions(-)

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 711e7b29b..2fe72d921 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -50,30 +50,32 @@ CPU_VARIANTS = {
 # GCC Flags ----------------------------------------------------------------------------------------
 
 GCC_FLAGS = {
-    #                               /---------- Base ISA
-    #                               |    /----- Hardware Multiply + Divide
-    #                               |    |/---- Atomics
-    #                               |    ||/--- Compressed ISA
-    #                               |    |||/-- Single-Precision Floating-Point
-    #                               |    ||||/- Double-Precision Floating-Point
-    #                               i    macfd
-    "minimal":          "-march=rv32i2p0       -mabi=ilp32",
-    "minimal+debug":    "-march=rv32i2p0       -mabi=ilp32",
-    "lite":             "-march=rv32i2p0_m     -mabi=ilp32",
-    "lite+debug":       "-march=rv32i2p0_m     -mabi=ilp32",
-    "standard":         "-march=rv32i2p0_m     -mabi=ilp32",
-    "standard+debug":   "-march=rv32i2p0_m     -mabi=ilp32",
-    "imac":             "-march=rv32i2p0_mac   -mabi=ilp32",
-    "imac+debug":       "-march=rv32i2p0_mac   -mabi=ilp32",
-    "full":             "-march=rv32i2p0_m     -mabi=ilp32",
-    "full+cfu":         "-march=rv32i2p0_m     -mabi=ilp32",
-    "full+debug":       "-march=rv32i2p0_m     -mabi=ilp32",
-    "full+cfu+debug":   "-march=rv32i2p0_m     -mabi=ilp32",
-    "linux":            "-march=rv32i2p0_ma    -mabi=ilp32",
-    "linux+debug":      "-march=rv32i2p0_ma    -mabi=ilp32",
-    "linux+no-dsp":     "-march=rv32i2p0_ma    -mabi=ilp32",
-    "secure":           "-march=rv32i2p0_ma    -mabi=ilp32",
-    "secure+debug":     "-march=rv32i2p0_ma    -mabi=ilp32",
+    #                                  /---------- Base ISA
+    #                                  |    /----- Hardware Multiply + Divide
+    #                                  |    |/---- Atomics
+    #                                  |    ||/--- Compressed ISA
+    #                                  |    |||/-- Single-Precision Floating-Point
+    #                                  |    ||||/- Double-Precision Floating-Point
+    #                                  i    macfd
+    "minimal":              "-march=rv32i2p0       -mabi=ilp32",
+    "minimal+debug":        "-march=rv32i2p0       -mabi=ilp32",
+    "minimal+debug+hwbp":   "-march=rv32i2p0       -mabi=ilp32",
+    "lite":                 "-march=rv32i2p0_m     -mabi=ilp32",
+    "lite+debug":           "-march=rv32i2p0_m     -mabi=ilp32",
+    "lite+debug+hwbp":      "-march=rv32i2p0_m     -mabi=ilp32",
+    "standard":             "-march=rv32i2p0_m     -mabi=ilp32",
+    "standard+debug":       "-march=rv32i2p0_m     -mabi=ilp32",
+    "imac":                 "-march=rv32i2p0_mac   -mabi=ilp32",
+    "imac+debug":           "-march=rv32i2p0_mac   -mabi=ilp32",
+    "full":                 "-march=rv32i2p0_m     -mabi=ilp32",
+    "full+cfu":             "-march=rv32i2p0_m     -mabi=ilp32",
+    "full+debug":           "-march=rv32i2p0_m     -mabi=ilp32",
+    "full+cfu+debug":       "-march=rv32i2p0_m     -mabi=ilp32",
+    "linux":                "-march=rv32i2p0_ma    -mabi=ilp32",
+    "linux+debug":          "-march=rv32i2p0_ma    -mabi=ilp32",
+    "linux+no-dsp":         "-march=rv32i2p0_ma    -mabi=ilp32",
+    "secure":               "-march=rv32i2p0_ma    -mabi=ilp32",
+    "secure+debug":         "-march=rv32i2p0_ma    -mabi=ilp32",
 }
 
 # VexRiscv Timer -----------------------------------------------------------------------------------