From 12b9c8b2e78245fb59c1eab94abad2cd4018d3c5 Mon Sep 17 00:00:00 2001 From: Meinhard Kissich Date: Mon, 4 Mar 2024 21:44:18 +0100 Subject: [PATCH] cpu/fazyrv: Fix minor path typo --- litex/soc/cores/cpu/fazyrv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/fazyrv/core.py b/litex/soc/cores/cpu/fazyrv/core.py index a7b7849ae..5081e5f7a 100644 --- a/litex/soc/cores/cpu/fazyrv/core.py +++ b/litex/soc/cores/cpu/fazyrv/core.py @@ -132,7 +132,7 @@ class FazyRV(CPU): @staticmethod def add_sources(platform, variant): - if not os.path.exists("FazyR"): + if not os.path.exists("FazyRV"): os.system(f"git clone https://github.com/meiniKi/FazyRV") vdir = "FazyRV/rtl" platform.add_verilog_include_path(vdir)