diff --git a/examples/basic_sim.py b/examples/basic_sim.py
index a4f17c465..035440ca3 100644
--- a/examples/basic_sim.py
+++ b/examples/basic_sim.py
@@ -13,6 +13,7 @@ class Counter:
 		else:
 			s.wr(self.ce, 1)
 		print("Cycle: " + str(s.cycle_counter) + " Count: " + str(s.rd(self.count)))
+	do_simulation.initialize = True
 	
 	def get_fragment(self):
 		sync = [If(self.ce, self.count.eq(self.count + 1))]
diff --git a/examples/memory_sim.py b/examples/memory_sim.py
index 7c58b2bbb..dae392572 100644
--- a/examples/memory_sim.py
+++ b/examples/memory_sim.py
@@ -10,11 +10,10 @@ class Mem:
 		self.mem = Memory(16, 2**12, p, init=list(range(20)))
 	
 	def do_simulation(self, s):
-		if s.cycle_counter >= 0:
-			value = s.rd(self.mem, s.cycle_counter)
-			print(value)
-			if value == 10:
-				s.interrupt = True
+		value = s.rd(self.mem, s.cycle_counter)
+		print(value)
+		if value == 10:
+			s.interrupt = True
 	
 	def get_fragment(self):
 		return Fragment(memories=[self.mem], sim=[self.do_simulation])
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index e5730ff50..69f53f65d 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -278,4 +278,5 @@ class Fragment:
 
 	def call_sim(self, simulator):
 		for s in self.sim:
-			s(simulator)
+			if simulator.cycle_counter >= 0 or (hasattr(s, "initialize") and s.initialize):
+				s(simulator)