From 996be957254164018c927d83ce8d041e8c24da96 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Nov 2020 12:49:43 +0100 Subject: [PATCH] tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki). --- litex/tools/litex_sim.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 8585b1ed0..ca126931d 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -281,6 +281,7 @@ class SimSoC(SoCCore): # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ + # IBus (could also just added as self.cpu.ibus) self.cpu.ibus.stb, self.cpu.ibus.cyc, self.cpu.ibus.adr, @@ -289,6 +290,15 @@ class SimSoC(SoCCore): self.cpu.ibus.sel, self.cpu.ibus.dat_w, self.cpu.ibus.dat_r, + # DBus (could also just added as self.cpu.dbus) + self.cpu.dbus.stb, + self.cpu.dbus.cyc, + self.cpu.dbus.adr, + self.cpu.dbus.we, + self.cpu.dbus.ack, + self.cpu.dbus.sel, + self.cpu.dbus.dat_w, + self.cpu.dbus.dat_r, ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, depth = 512,