From 99a78b8e3301af62857bdd6e39601b214979c7a9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 22 Mar 2013 13:50:16 +0100 Subject: [PATCH] clean up --- examples/de0_nano/client/test_mila.py | 2 -- miscope/bridges/spi2csr/__init__.py | 8 ++++---- miscope/bridges/uart2csr/__init__.py | 2 +- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/examples/de0_nano/client/test_mila.py b/examples/de0_nano/client/test_mila.py index 2b9049255..4887851bb 100644 --- a/examples/de0_nano/client/test_mila.py +++ b/examples/de0_nano/client/test_mila.py @@ -31,8 +31,6 @@ mila = mila.MiLa(MILA_ADDR, trigger, recorder, csr) dat_vcd = VcdDat(dat_w) def capture(size): - global trigger - global recorder global dat_vcd sum_tt = gen_truth_table("term") mila.trigger.sum.set(sum_tt) diff --git a/miscope/bridges/spi2csr/__init__.py b/miscope/bridges/spi2csr/__init__.py index d396fa687..2416cb6c1 100644 --- a/miscope/bridges/spi2csr/__init__.py +++ b/miscope/bridges/spi2csr/__init__.py @@ -4,13 +4,13 @@ from migen.genlib.cdc import * from migen.bus import csr class Spi2Csr(Module): - def __init__(self, a_w, d_w, burst_length=8): - self.a_w = a_w - self.d_w = d_w + def __init__(self, burst_length=8): + self.a_w = 14 + self.d_w = 8 self.burst_length = 8 # Csr interface - self.csr = csr.Interface(self.a_w, self.d_w) + self.csr = csr.Interface() # Spi interface self.spi_clk = Signal() diff --git a/miscope/bridges/uart2csr/__init__.py b/miscope/bridges/uart2csr/__init__.py index 9cf0a8b4e..a9c20fa61 100644 --- a/miscope/bridges/uart2csr/__init__.py +++ b/miscope/bridges/uart2csr/__init__.py @@ -16,7 +16,7 @@ class Uart2Csr(Module): self.tx = Signal() # Csr interface - self.csr = csr.Interface(32, 8) + self.csr = csr.Interface() ###