From 9a6447172aaf824daff47345fe665461f3110bd1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 9 Nov 2018 15:42:34 +0100 Subject: [PATCH] soc/integration/soc_sdram: allow using axi interface with litedram --- litex/soc/integration/soc_sdram.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 71789a4fe..432de0b26 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -5,7 +5,8 @@ from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import AutoCSR from litex.soc.integration.soc_core import * -from litedram.frontend.wishbone import LiteDRAMWishbone2Native +from litedram.frontend.wishbone import * +from litedram.frontend.axi import * from litedram import dfii, core @@ -51,7 +52,7 @@ class SoCSDRAM(SoCCore): raise FinalizeError self._wb_sdram_ifs.append(interface) - def register_sdram(self, phy, geom_settings, timing_settings, **kwargs): + def register_sdram(self, phy, geom_settings, timing_settings, use_axi=False, **kwargs): assert not self._sdram_phy self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning @@ -84,7 +85,15 @@ class SoCSDRAM(SoCCore): self.submodules.l2_cache = FullMemoryWE()(l2_cache) else: self.submodules.l2_cache = l2_cache - self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) + if use_axi: + axi_port = LiteDRAMAXIPort( + port.data_width, + port.address_width + log2_int(port.data_width//8)) + axi2native = LiteDRAMAXI2Native(axi_port, port) + self.submodules += axi2native + self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port) + else: + self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port) def do_finalize(self): if not self.integrated_main_ram_size: