From 9b08b037e41f3bb37f038b7e8eb1fcdbe8c31608 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 24 Sep 2015 15:59:55 +0800 Subject: [PATCH] break down sdram, improve consistency of core names --- misoc/cores/{sdram/phy => }/dfii.py | 0 .../{dvisampler => dvi_sampler}/__init__.py | 0 .../{dvisampler => dvi_sampler}/analysis.py | 0 .../{dvisampler => dvi_sampler}/chansync.py | 0 .../{dvisampler => dvi_sampler}/charsync.py | 0 .../{dvisampler => dvi_sampler}/clocking.py | 0 .../{dvisampler => dvi_sampler}/common.py | 0 .../cores/{dvisampler => dvi_sampler}/core.py | 0 .../datacapture.py | 0 .../{dvisampler => dvi_sampler}/debug.py | 0 .../{dvisampler => dvi_sampler}/decoding.py | 0 .../cores/{dvisampler => dvi_sampler}/dma.py | 0 .../cores/{dvisampler => dvi_sampler}/edid.py | 0 .../cores/{dvisampler => dvi_sampler}/wer.py | 0 .../{liteethmini => lasmicon}/__init__.py | 0 .../{sdram/core => }/lasmicon/bankmachine.py | 0 .../lasmicon/__init__.py => lasmicon/core.py} | 0 .../{sdram/core => }/lasmicon/multiplexer.py | 0 misoc/cores/{sdram/core => }/lasmicon/perf.py | 0 .../{sdram/core => }/lasmicon/refresher.py | 0 .../test_bankmachine.py} | 2 +- .../common.py => lasmicon/test_common.py} | 0 .../lasmicon_df_tb.py => lasmicon/test_df.py} | 2 +- .../lasmicon_tb.py => lasmicon/test_lasmi.py} | 2 +- .../test_refresher.py} | 0 .../lasmicon_wb.py => lasmicon/test_wb.py} | 2 +- .../{liteethmini => liteeth_mini}/LICENSE | 0 .../{liteethmini => liteeth_mini}/README | 0 .../mac/frontend => liteeth_mini}/__init__.py | 0 .../{liteethmini => liteeth_mini}/common.py | 0 .../mac/__init__.py | 0 .../mac/core/__init__.py | 0 .../mac/core/crc.py | 0 .../mac/core/gap.py | 0 .../mac/core/last_be.py | 0 .../mac/core/padding.py | 0 .../mac/core/preamble.py | 0 .../mac}/frontend/__init__.py | 0 .../mac/frontend/sram.py | 0 .../mac/frontend/wishbone.py | 0 .../phy/__init__.py | 0 .../{liteethmini => liteeth_mini}/phy/gmii.py | 0 .../phy/gmii_mii.py | 0 .../phy/loopback.py | 0 .../{liteethmini => liteeth_mini}/phy/mii.py | 0 .../phy/s6rgmii.py | 0 .../{liteethmini => liteeth_mini}/phy/sim.py | 0 misoc/cores/minicon/__init__.py | 1 + .../minicon/__init__.py => minicon/core.py} | 1 - .../test/minicon_tb.py => minicon/test.py} | 0 .../cores/{norflash16.py => nor_flash_16.py} | 0 misoc/cores/sdram/__init__.py | 11 ----- misoc/cores/sdram/core/__init__.py | 36 ---------------- misoc/cores/sdram/phy/__init__.py | 0 .../sdram/test/abstract_transactions_lasmi.py | 42 ------------------- .../{sdram/phy/simphy.py => sdram_model.py} | 1 - misoc/cores/sdram_phy/__init__.py | 3 ++ .../{sdram/phy => sdram_phy}/gensdrphy.py | 0 .../{sdram/phy => sdram_phy}/k7ddrphy.py | 0 .../{sdram/phy => sdram_phy}/s6ddrphy.py | 0 .../{sdram/module.py => sdram_settings.py} | 29 ++++++++----- .../frontend/memtest.py => sdram_tester.py} | 0 misoc/cores/{spiflash.py => spi_flash.py} | 0 .../{cpuif.py => cpu_interface.py} | 0 .../sdram_init.py} | 0 misoc/integration/soc_sdram.py | 30 ++++++++++++- .../{cores/sdram/phy => interconnect}/dfi.py | 0 .../frontend => interconnect}/dma_lasmi.py | 0 .../sdram/core => interconnect}/lasmibus.py | 0 .../sdram/core => interconnect}/lasmixbar.py | 0 .../wishbone2lasmi.py | 0 71 files changed, 55 insertions(+), 107 deletions(-) rename misoc/cores/{sdram/phy => }/dfii.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/__init__.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/analysis.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/chansync.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/charsync.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/clocking.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/common.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/core.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/datacapture.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/debug.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/decoding.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/dma.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/edid.py (100%) rename misoc/cores/{dvisampler => dvi_sampler}/wer.py (100%) rename misoc/cores/{liteethmini => lasmicon}/__init__.py (100%) rename misoc/cores/{sdram/core => }/lasmicon/bankmachine.py (100%) rename misoc/cores/{sdram/core/lasmicon/__init__.py => lasmicon/core.py} (100%) rename misoc/cores/{sdram/core => }/lasmicon/multiplexer.py (100%) rename misoc/cores/{sdram/core => }/lasmicon/perf.py (100%) rename misoc/cores/{sdram/core => }/lasmicon/refresher.py (100%) rename misoc/cores/{sdram/test/bankmachine_tb.py => lasmicon/test_bankmachine.py} (94%) rename misoc/cores/{sdram/test/common.py => lasmicon/test_common.py} (100%) rename misoc/cores/{sdram/test/lasmicon_df_tb.py => lasmicon/test_df.py} (95%) rename misoc/cores/{sdram/test/lasmicon_tb.py => lasmicon/test_lasmi.py} (94%) rename misoc/cores/{sdram/test/refresher.py => lasmicon/test_refresher.py} (100%) rename misoc/cores/{sdram/test/lasmicon_wb.py => lasmicon/test_wb.py} (94%) rename misoc/cores/{liteethmini => liteeth_mini}/LICENSE (100%) rename misoc/cores/{liteethmini => liteeth_mini}/README (100%) rename misoc/cores/{liteethmini/mac/frontend => liteeth_mini}/__init__.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/common.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/__init__.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/core/__init__.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/core/crc.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/core/gap.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/core/last_be.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/core/padding.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/core/preamble.py (100%) rename misoc/cores/{sdram => liteeth_mini/mac}/frontend/__init__.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/frontend/sram.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/mac/frontend/wishbone.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/phy/__init__.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/phy/gmii.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/phy/gmii_mii.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/phy/loopback.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/phy/mii.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/phy/s6rgmii.py (100%) rename misoc/cores/{liteethmini => liteeth_mini}/phy/sim.py (100%) create mode 100644 misoc/cores/minicon/__init__.py rename misoc/cores/{sdram/core/minicon/__init__.py => minicon/core.py} (99%) rename misoc/cores/{sdram/test/minicon_tb.py => minicon/test.py} (100%) rename misoc/cores/{norflash16.py => nor_flash_16.py} (100%) delete mode 100644 misoc/cores/sdram/__init__.py delete mode 100644 misoc/cores/sdram/core/__init__.py delete mode 100644 misoc/cores/sdram/phy/__init__.py delete mode 100644 misoc/cores/sdram/test/abstract_transactions_lasmi.py rename misoc/cores/{sdram/phy/simphy.py => sdram_model.py} (99%) create mode 100644 misoc/cores/sdram_phy/__init__.py rename misoc/cores/{sdram/phy => sdram_phy}/gensdrphy.py (100%) rename misoc/cores/{sdram/phy => sdram_phy}/k7ddrphy.py (100%) rename misoc/cores/{sdram/phy => sdram_phy}/s6ddrphy.py (100%) rename misoc/cores/{sdram/module.py => sdram_settings.py} (88%) rename misoc/cores/{sdram/frontend/memtest.py => sdram_tester.py} (100%) rename misoc/cores/{spiflash.py => spi_flash.py} (100%) rename misoc/integration/{cpuif.py => cpu_interface.py} (100%) rename misoc/{cores/sdram/phy/initsequence.py => integration/sdram_init.py} (100%) rename misoc/{cores/sdram/phy => interconnect}/dfi.py (100%) rename misoc/{cores/sdram/frontend => interconnect}/dma_lasmi.py (100%) rename misoc/{cores/sdram/core => interconnect}/lasmibus.py (100%) rename misoc/{cores/sdram/core => interconnect}/lasmixbar.py (100%) rename misoc/{cores/sdram/frontend => interconnect}/wishbone2lasmi.py (100%) diff --git a/misoc/cores/sdram/phy/dfii.py b/misoc/cores/dfii.py similarity index 100% rename from misoc/cores/sdram/phy/dfii.py rename to misoc/cores/dfii.py diff --git a/misoc/cores/dvisampler/__init__.py b/misoc/cores/dvi_sampler/__init__.py similarity index 100% rename from misoc/cores/dvisampler/__init__.py rename to misoc/cores/dvi_sampler/__init__.py diff --git a/misoc/cores/dvisampler/analysis.py b/misoc/cores/dvi_sampler/analysis.py similarity index 100% rename from misoc/cores/dvisampler/analysis.py rename to misoc/cores/dvi_sampler/analysis.py diff --git a/misoc/cores/dvisampler/chansync.py b/misoc/cores/dvi_sampler/chansync.py similarity index 100% rename from misoc/cores/dvisampler/chansync.py rename to misoc/cores/dvi_sampler/chansync.py diff --git a/misoc/cores/dvisampler/charsync.py b/misoc/cores/dvi_sampler/charsync.py similarity index 100% rename from misoc/cores/dvisampler/charsync.py rename to misoc/cores/dvi_sampler/charsync.py diff --git a/misoc/cores/dvisampler/clocking.py b/misoc/cores/dvi_sampler/clocking.py similarity index 100% rename from misoc/cores/dvisampler/clocking.py rename to misoc/cores/dvi_sampler/clocking.py diff --git a/misoc/cores/dvisampler/common.py b/misoc/cores/dvi_sampler/common.py similarity index 100% rename from misoc/cores/dvisampler/common.py rename to misoc/cores/dvi_sampler/common.py diff --git a/misoc/cores/dvisampler/core.py b/misoc/cores/dvi_sampler/core.py similarity index 100% rename from misoc/cores/dvisampler/core.py rename to misoc/cores/dvi_sampler/core.py diff --git a/misoc/cores/dvisampler/datacapture.py b/misoc/cores/dvi_sampler/datacapture.py similarity index 100% rename from misoc/cores/dvisampler/datacapture.py rename to misoc/cores/dvi_sampler/datacapture.py diff --git a/misoc/cores/dvisampler/debug.py b/misoc/cores/dvi_sampler/debug.py similarity index 100% rename from misoc/cores/dvisampler/debug.py rename to misoc/cores/dvi_sampler/debug.py diff --git a/misoc/cores/dvisampler/decoding.py b/misoc/cores/dvi_sampler/decoding.py similarity index 100% rename from misoc/cores/dvisampler/decoding.py rename to misoc/cores/dvi_sampler/decoding.py diff --git a/misoc/cores/dvisampler/dma.py b/misoc/cores/dvi_sampler/dma.py similarity index 100% rename from misoc/cores/dvisampler/dma.py rename to misoc/cores/dvi_sampler/dma.py diff --git a/misoc/cores/dvisampler/edid.py b/misoc/cores/dvi_sampler/edid.py similarity index 100% rename from misoc/cores/dvisampler/edid.py rename to misoc/cores/dvi_sampler/edid.py diff --git a/misoc/cores/dvisampler/wer.py b/misoc/cores/dvi_sampler/wer.py similarity index 100% rename from misoc/cores/dvisampler/wer.py rename to misoc/cores/dvi_sampler/wer.py diff --git a/misoc/cores/liteethmini/__init__.py b/misoc/cores/lasmicon/__init__.py similarity index 100% rename from misoc/cores/liteethmini/__init__.py rename to misoc/cores/lasmicon/__init__.py diff --git a/misoc/cores/sdram/core/lasmicon/bankmachine.py b/misoc/cores/lasmicon/bankmachine.py similarity index 100% rename from misoc/cores/sdram/core/lasmicon/bankmachine.py rename to misoc/cores/lasmicon/bankmachine.py diff --git a/misoc/cores/sdram/core/lasmicon/__init__.py b/misoc/cores/lasmicon/core.py similarity index 100% rename from misoc/cores/sdram/core/lasmicon/__init__.py rename to misoc/cores/lasmicon/core.py diff --git a/misoc/cores/sdram/core/lasmicon/multiplexer.py b/misoc/cores/lasmicon/multiplexer.py similarity index 100% rename from misoc/cores/sdram/core/lasmicon/multiplexer.py rename to misoc/cores/lasmicon/multiplexer.py diff --git a/misoc/cores/sdram/core/lasmicon/perf.py b/misoc/cores/lasmicon/perf.py similarity index 100% rename from misoc/cores/sdram/core/lasmicon/perf.py rename to misoc/cores/lasmicon/perf.py diff --git a/misoc/cores/sdram/core/lasmicon/refresher.py b/misoc/cores/lasmicon/refresher.py similarity index 100% rename from misoc/cores/sdram/core/lasmicon/refresher.py rename to misoc/cores/lasmicon/refresher.py diff --git a/misoc/cores/sdram/test/bankmachine_tb.py b/misoc/cores/lasmicon/test_bankmachine.py similarity index 94% rename from misoc/cores/sdram/test/bankmachine_tb.py rename to misoc/cores/lasmicon/test_bankmachine.py index 020d12685..f6f03405b 100644 --- a/misoc/cores/sdram/test/bankmachine_tb.py +++ b/misoc/cores/lasmicon/test_bankmachine.py @@ -4,7 +4,7 @@ from migen.sim.generic import run_simulation from misoc.mem.sdram.code import lasmibus from misoc.mem.sdram.core.lasmicon.bankmachine import * -from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger +from test_common import sdram_phy, sdram_geom, sdram_timing, CommandLogger def my_generator(): diff --git a/misoc/cores/sdram/test/common.py b/misoc/cores/lasmicon/test_common.py similarity index 100% rename from misoc/cores/sdram/test/common.py rename to misoc/cores/lasmicon/test_common.py diff --git a/misoc/cores/sdram/test/lasmicon_df_tb.py b/misoc/cores/lasmicon/test_df.py similarity index 95% rename from misoc/cores/sdram/test/lasmicon_df_tb.py rename to misoc/cores/lasmicon/test_df.py index 326d56a17..588bd67f7 100644 --- a/misoc/cores/sdram/test/lasmicon_df_tb.py +++ b/misoc/cores/lasmicon/test_df.py @@ -5,7 +5,7 @@ from misoc.mem.sdram.core import lasmibus from misoc.mem.sdram.core.lasmicon import * from misoc.mem.sdram.frontend import dma_lasmi -from common import sdram_phy, sdram_geom, sdram_timing, DFILogger +from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger class TB(Module): diff --git a/misoc/cores/sdram/test/lasmicon_tb.py b/misoc/cores/lasmicon/test_lasmi.py similarity index 94% rename from misoc/cores/sdram/test/lasmicon_tb.py rename to misoc/cores/lasmicon/test_lasmi.py index 469f8eb8f..b81f14db4 100644 --- a/misoc/cores/sdram/test/lasmicon_tb.py +++ b/misoc/cores/lasmicon/test_lasmi.py @@ -4,7 +4,7 @@ from migen.sim.generic import run_simulation from misoc.mem.sdram.core import lasmibus from misoc.mem.sdram.core.lasmicon import * -from common import sdram_phy, sdram_geom, sdram_timing, DFILogger +from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger def my_generator_r(n): diff --git a/misoc/cores/sdram/test/refresher.py b/misoc/cores/lasmicon/test_refresher.py similarity index 100% rename from misoc/cores/sdram/test/refresher.py rename to misoc/cores/lasmicon/test_refresher.py diff --git a/misoc/cores/sdram/test/lasmicon_wb.py b/misoc/cores/lasmicon/test_wb.py similarity index 94% rename from misoc/cores/sdram/test/lasmicon_wb.py rename to misoc/cores/lasmicon/test_wb.py index 37c5b031a..abbaed9ae 100644 --- a/misoc/cores/sdram/test/lasmicon_wb.py +++ b/misoc/cores/lasmicon/test_wb.py @@ -7,7 +7,7 @@ from misoc.mem.sdram.core import lasmibus from misoc.mem.sdram.core.lasmicon import * from misoc.mem.sdram.frontend import wishbone2lasmi -from common import sdram_phy, sdram_geom, sdram_timing, DFILogger +from test_common import sdram_phy, sdram_geom, sdram_timing, DFILogger l2_size = 8192 # in bytes diff --git a/misoc/cores/liteethmini/LICENSE b/misoc/cores/liteeth_mini/LICENSE similarity index 100% rename from misoc/cores/liteethmini/LICENSE rename to misoc/cores/liteeth_mini/LICENSE diff --git a/misoc/cores/liteethmini/README b/misoc/cores/liteeth_mini/README similarity index 100% rename from misoc/cores/liteethmini/README rename to misoc/cores/liteeth_mini/README diff --git a/misoc/cores/liteethmini/mac/frontend/__init__.py b/misoc/cores/liteeth_mini/__init__.py similarity index 100% rename from misoc/cores/liteethmini/mac/frontend/__init__.py rename to misoc/cores/liteeth_mini/__init__.py diff --git a/misoc/cores/liteethmini/common.py b/misoc/cores/liteeth_mini/common.py similarity index 100% rename from misoc/cores/liteethmini/common.py rename to misoc/cores/liteeth_mini/common.py diff --git a/misoc/cores/liteethmini/mac/__init__.py b/misoc/cores/liteeth_mini/mac/__init__.py similarity index 100% rename from misoc/cores/liteethmini/mac/__init__.py rename to misoc/cores/liteeth_mini/mac/__init__.py diff --git a/misoc/cores/liteethmini/mac/core/__init__.py b/misoc/cores/liteeth_mini/mac/core/__init__.py similarity index 100% rename from misoc/cores/liteethmini/mac/core/__init__.py rename to misoc/cores/liteeth_mini/mac/core/__init__.py diff --git a/misoc/cores/liteethmini/mac/core/crc.py b/misoc/cores/liteeth_mini/mac/core/crc.py similarity index 100% rename from misoc/cores/liteethmini/mac/core/crc.py rename to misoc/cores/liteeth_mini/mac/core/crc.py diff --git a/misoc/cores/liteethmini/mac/core/gap.py b/misoc/cores/liteeth_mini/mac/core/gap.py similarity index 100% rename from misoc/cores/liteethmini/mac/core/gap.py rename to misoc/cores/liteeth_mini/mac/core/gap.py diff --git a/misoc/cores/liteethmini/mac/core/last_be.py b/misoc/cores/liteeth_mini/mac/core/last_be.py similarity index 100% rename from misoc/cores/liteethmini/mac/core/last_be.py rename to misoc/cores/liteeth_mini/mac/core/last_be.py diff --git a/misoc/cores/liteethmini/mac/core/padding.py b/misoc/cores/liteeth_mini/mac/core/padding.py similarity index 100% rename from misoc/cores/liteethmini/mac/core/padding.py rename to misoc/cores/liteeth_mini/mac/core/padding.py diff --git a/misoc/cores/liteethmini/mac/core/preamble.py b/misoc/cores/liteeth_mini/mac/core/preamble.py similarity index 100% rename from misoc/cores/liteethmini/mac/core/preamble.py rename to misoc/cores/liteeth_mini/mac/core/preamble.py diff --git a/misoc/cores/sdram/frontend/__init__.py b/misoc/cores/liteeth_mini/mac/frontend/__init__.py similarity index 100% rename from misoc/cores/sdram/frontend/__init__.py rename to misoc/cores/liteeth_mini/mac/frontend/__init__.py diff --git a/misoc/cores/liteethmini/mac/frontend/sram.py b/misoc/cores/liteeth_mini/mac/frontend/sram.py similarity index 100% rename from misoc/cores/liteethmini/mac/frontend/sram.py rename to misoc/cores/liteeth_mini/mac/frontend/sram.py diff --git a/misoc/cores/liteethmini/mac/frontend/wishbone.py b/misoc/cores/liteeth_mini/mac/frontend/wishbone.py similarity index 100% rename from misoc/cores/liteethmini/mac/frontend/wishbone.py rename to misoc/cores/liteeth_mini/mac/frontend/wishbone.py diff --git a/misoc/cores/liteethmini/phy/__init__.py b/misoc/cores/liteeth_mini/phy/__init__.py similarity index 100% rename from misoc/cores/liteethmini/phy/__init__.py rename to misoc/cores/liteeth_mini/phy/__init__.py diff --git a/misoc/cores/liteethmini/phy/gmii.py b/misoc/cores/liteeth_mini/phy/gmii.py similarity index 100% rename from misoc/cores/liteethmini/phy/gmii.py rename to misoc/cores/liteeth_mini/phy/gmii.py diff --git a/misoc/cores/liteethmini/phy/gmii_mii.py b/misoc/cores/liteeth_mini/phy/gmii_mii.py similarity index 100% rename from misoc/cores/liteethmini/phy/gmii_mii.py rename to misoc/cores/liteeth_mini/phy/gmii_mii.py diff --git a/misoc/cores/liteethmini/phy/loopback.py b/misoc/cores/liteeth_mini/phy/loopback.py similarity index 100% rename from misoc/cores/liteethmini/phy/loopback.py rename to misoc/cores/liteeth_mini/phy/loopback.py diff --git a/misoc/cores/liteethmini/phy/mii.py b/misoc/cores/liteeth_mini/phy/mii.py similarity index 100% rename from misoc/cores/liteethmini/phy/mii.py rename to misoc/cores/liteeth_mini/phy/mii.py diff --git a/misoc/cores/liteethmini/phy/s6rgmii.py b/misoc/cores/liteeth_mini/phy/s6rgmii.py similarity index 100% rename from misoc/cores/liteethmini/phy/s6rgmii.py rename to misoc/cores/liteeth_mini/phy/s6rgmii.py diff --git a/misoc/cores/liteethmini/phy/sim.py b/misoc/cores/liteeth_mini/phy/sim.py similarity index 100% rename from misoc/cores/liteethmini/phy/sim.py rename to misoc/cores/liteeth_mini/phy/sim.py diff --git a/misoc/cores/minicon/__init__.py b/misoc/cores/minicon/__init__.py new file mode 100644 index 000000000..5b423e41f --- /dev/null +++ b/misoc/cores/minicon/__init__.py @@ -0,0 +1 @@ +from misoc.cores.minicon.core import Minicon, MiniconSettings diff --git a/misoc/cores/sdram/core/minicon/__init__.py b/misoc/cores/minicon/core.py similarity index 99% rename from misoc/cores/sdram/core/minicon/__init__.py rename to misoc/cores/minicon/core.py index dcb48e5dd..3be6d1789 100644 --- a/misoc/cores/sdram/core/minicon/__init__.py +++ b/misoc/cores/minicon/core.py @@ -96,7 +96,6 @@ class Minicon(Module): address_align) # Manage banks - bank_open = Signal() bank_idle = Signal() bank_hit = Signal() diff --git a/misoc/cores/sdram/test/minicon_tb.py b/misoc/cores/minicon/test.py similarity index 100% rename from misoc/cores/sdram/test/minicon_tb.py rename to misoc/cores/minicon/test.py diff --git a/misoc/cores/norflash16.py b/misoc/cores/nor_flash_16.py similarity index 100% rename from misoc/cores/norflash16.py rename to misoc/cores/nor_flash_16.py diff --git a/misoc/cores/sdram/__init__.py b/misoc/cores/sdram/__init__.py deleted file mode 100644 index b327bb080..000000000 --- a/misoc/cores/sdram/__init__.py +++ /dev/null @@ -1,11 +0,0 @@ -from collections import namedtuple - -PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency") -def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0): - return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency) - -GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits") -def GeomSettings(bankbits, rowbits, colbits): - return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits)) - -TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC") diff --git a/misoc/cores/sdram/core/__init__.py b/misoc/cores/sdram/core/__init__.py deleted file mode 100644 index 6d7057f1b..000000000 --- a/misoc/cores/sdram/core/__init__.py +++ /dev/null @@ -1,36 +0,0 @@ -from migen import * -from migen.genlib.record import * -from migen.bank.description import * - -from misoc.mem.sdram.phy import dfii -from misoc.mem.sdram.core import minicon, lasmicon -from misoc.mem.sdram.core import lasmixbar - - -class SDRAMCore(Module, AutoCSR): - def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs): - # DFI - self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits, - phy.settings.dfi_databits, phy.settings.nphases) - self.comb += Record.connect(self.dfii.master, phy.dfi) - - # LASMICON - if isinstance(controller_settings, lasmicon.LASMIconSettings): - self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, - geom_settings, - timing_settings, - controller_settings, - **kwargs) - self.comb += Record.connect(controller.dfi, self.dfii.slave) - - self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic], - controller.nrowbits) - - # MINICON - elif isinstance(controller_settings, minicon.MiniconSettings): - self.submodules.controller = controller = minicon.Minicon(phy.settings, - geom_settings, - timing_settings) - self.comb += Record.connect(controller.dfi, self.dfii.slave) - else: - raise ValueError("Unsupported SDRAM controller type") diff --git a/misoc/cores/sdram/phy/__init__.py b/misoc/cores/sdram/phy/__init__.py deleted file mode 100644 index e69de29bb..000000000 diff --git a/misoc/cores/sdram/test/abstract_transactions_lasmi.py b/misoc/cores/sdram/test/abstract_transactions_lasmi.py deleted file mode 100644 index 18d77963a..000000000 --- a/misoc/cores/sdram/test/abstract_transactions_lasmi.py +++ /dev/null @@ -1,42 +0,0 @@ -from migen import * -from migen.bus.transactions import * -from migen.sim.generic import run_simulation - -from misoc.mem.sdram.core import lasmibus - - -def my_generator(n): - bank = n % 4 - for x in range(4): - t = TWrite(4*bank+x, 0x1000*bank + 0x100*x) - yield t - print("{0}: Wrote in {1} cycle(s)".format(n, t.latency)) - - for x in range(4): - t = TRead(4*bank+x) - yield t - print("{0}: Read {1:x} in {2} cycle(s)".format(n, t.data, t.latency)) - assert(t.data == 0x1000*bank + 0x100*x) - - -class MyModel(lasmibus.TargetModel): - def read(self, bank, address): - r = 0x1000*bank + 0x100*address - #print("read from bank {0} address {1} -> {2:x}".format(bank, address, r)) - return r - - def write(self, bank, address, data, we): - print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data)) - assert(data == 0x1000*bank + 0x100*address) - - -class TB(Module): - def __init__(self): - self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4, - read_latency=4, write_latency=1) - self.submodules.xbar = lasmibus.Crossbar([self.controller.bus], 2) - self.initiators = [lasmibus.Initiator(my_generator(n), self.xbar.get_master()) for n in range(4)] - self.submodules += self.initiators - -if __name__ == "__main__": - run_simulation(TB()) diff --git a/misoc/cores/sdram/phy/simphy.py b/misoc/cores/sdram_model.py similarity index 99% rename from misoc/cores/sdram/phy/simphy.py rename to misoc/cores/sdram_model.py index 6b8bcf192..28bcab11b 100644 --- a/misoc/cores/sdram/phy/simphy.py +++ b/misoc/cores/sdram_model.py @@ -158,7 +158,6 @@ class SDRAMPHYSim(Module): # bank reads reads = Signal(len(phases)) - read_data = Signal(data_width) cases = {} for np, phase in enumerate(phases): self.comb += reads[np].eq(phase.read) diff --git a/misoc/cores/sdram_phy/__init__.py b/misoc/cores/sdram_phy/__init__.py new file mode 100644 index 000000000..3cfda989b --- /dev/null +++ b/misoc/cores/sdram_phy/__init__.py @@ -0,0 +1,3 @@ +from misoc.cores.sdramphy.gensdrphy import GENSDRPHY +from misoc.cores.sdramphy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY +from misoc.cores.sdramphy.k7ddrphy import K7DDRPHY diff --git a/misoc/cores/sdram/phy/gensdrphy.py b/misoc/cores/sdram_phy/gensdrphy.py similarity index 100% rename from misoc/cores/sdram/phy/gensdrphy.py rename to misoc/cores/sdram_phy/gensdrphy.py diff --git a/misoc/cores/sdram/phy/k7ddrphy.py b/misoc/cores/sdram_phy/k7ddrphy.py similarity index 100% rename from misoc/cores/sdram/phy/k7ddrphy.py rename to misoc/cores/sdram_phy/k7ddrphy.py diff --git a/misoc/cores/sdram/phy/s6ddrphy.py b/misoc/cores/sdram_phy/s6ddrphy.py similarity index 100% rename from misoc/cores/sdram/phy/s6ddrphy.py rename to misoc/cores/sdram_phy/s6ddrphy.py diff --git a/misoc/cores/sdram/module.py b/misoc/cores/sdram_settings.py similarity index 88% rename from misoc/cores/sdram/module.py rename to misoc/cores/sdram_settings.py index bf1ce74fc..f6f6c7d51 100644 --- a/misoc/cores/sdram/module.py +++ b/misoc/cores/sdram_settings.py @@ -1,9 +1,21 @@ -# SDRAM memory modules library -# -# This library avoid duplications of memory modules definitions in targets and -# ease SDRAM usage. (User can only select an already existing module or create -# one for its board and contribute to this library) -# +from math import ceil +from collections import namedtuple + +from migen import * +from misoc.mem import sdram + + +PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency") +def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0): + return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency) + +GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits") +def GeomSettings(bankbits, rowbits, colbits): + return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits)) + +TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC") + + # TODO: # Try to share the maximum information we can between modules: # - ex: MT46V32M16 and MT46H32M16 are almost identical (V=DDR, H=LPDDR) @@ -14,11 +26,6 @@ # - Modules can have different speedgrades, add support for it (and also add # a check to verify clk_freq is in the supported range) -from math import ceil - -from migen import * -from misoc.mem import sdram - class SDRAMModule: def __init__(self, clk_freq, memtype, geom_settings, timing_settings): diff --git a/misoc/cores/sdram/frontend/memtest.py b/misoc/cores/sdram_tester.py similarity index 100% rename from misoc/cores/sdram/frontend/memtest.py rename to misoc/cores/sdram_tester.py diff --git a/misoc/cores/spiflash.py b/misoc/cores/spi_flash.py similarity index 100% rename from misoc/cores/spiflash.py rename to misoc/cores/spi_flash.py diff --git a/misoc/integration/cpuif.py b/misoc/integration/cpu_interface.py similarity index 100% rename from misoc/integration/cpuif.py rename to misoc/integration/cpu_interface.py diff --git a/misoc/cores/sdram/phy/initsequence.py b/misoc/integration/sdram_init.py similarity index 100% rename from misoc/cores/sdram/phy/initsequence.py rename to misoc/integration/sdram_init.py diff --git a/misoc/integration/soc_sdram.py b/misoc/integration/soc_sdram.py index 3e048c7f4..88e56b8ba 100644 --- a/misoc/integration/soc_sdram.py +++ b/misoc/integration/soc_sdram.py @@ -2,13 +2,41 @@ from migen import * from migen.bus import wishbone from migen.genlib.record import * -from misoc.mem.sdram.core import SDRAMCore from misoc.mem.sdram.core.lasmicon import LASMIconSettings from misoc.mem.sdram.core.minicon import MiniconSettings from misoc.mem.sdram.frontend import memtest, wishbone2lasmi from misoc.integration.soc_core import SoCCore +class SDRAMCore(Module, AutoCSR): + def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs): + # DFI + self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits, + phy.settings.dfi_databits, phy.settings.nphases) + self.comb += Record.connect(self.dfii.master, phy.dfi) + + # LASMICON + if isinstance(controller_settings, lasmicon.LASMIconSettings): + self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, + geom_settings, + timing_settings, + controller_settings, + **kwargs) + self.comb += Record.connect(controller.dfi, self.dfii.slave) + + self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic], + controller.nrowbits) + + # MINICON + elif isinstance(controller_settings, minicon.MiniconSettings): + self.submodules.controller = controller = minicon.Minicon(phy.settings, + geom_settings, + timing_settings) + self.comb += Record.connect(controller.dfi, self.dfii.slave) + else: + raise ValueError("Unsupported SDRAM controller type") + + class SoCSDRAM(SoCCore): csr_map = { "sdram": 8, diff --git a/misoc/cores/sdram/phy/dfi.py b/misoc/interconnect/dfi.py similarity index 100% rename from misoc/cores/sdram/phy/dfi.py rename to misoc/interconnect/dfi.py diff --git a/misoc/cores/sdram/frontend/dma_lasmi.py b/misoc/interconnect/dma_lasmi.py similarity index 100% rename from misoc/cores/sdram/frontend/dma_lasmi.py rename to misoc/interconnect/dma_lasmi.py diff --git a/misoc/cores/sdram/core/lasmibus.py b/misoc/interconnect/lasmibus.py similarity index 100% rename from misoc/cores/sdram/core/lasmibus.py rename to misoc/interconnect/lasmibus.py diff --git a/misoc/cores/sdram/core/lasmixbar.py b/misoc/interconnect/lasmixbar.py similarity index 100% rename from misoc/cores/sdram/core/lasmixbar.py rename to misoc/interconnect/lasmixbar.py diff --git a/misoc/cores/sdram/frontend/wishbone2lasmi.py b/misoc/interconnect/wishbone2lasmi.py similarity index 100% rename from misoc/cores/sdram/frontend/wishbone2lasmi.py rename to misoc/interconnect/wishbone2lasmi.py