diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index ca4aae2bc..81802f345 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -47,8 +47,8 @@ class Microwatt(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
-        self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=28)
+        self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=29)
+        self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=29)
         self.periph_buses = [wb_insn, wb_data]
         self.memory_buses = []
 
@@ -64,7 +64,7 @@ class Microwatt(CPU):
             i_wishbone_insn_ack   = wb_insn.ack,
             i_wishbone_insn_stall = wb_insn.cyc & ~wb_insn.ack, # No burst support
 
-            o_wishbone_insn_adr   = Cat(Signal(4), wb_insn.adr),
+            o_wishbone_insn_adr   = Cat(Signal(3), wb_insn.adr),
             o_wishbone_insn_dat_w = wb_insn.dat_w,
             o_wishbone_insn_cyc   = wb_insn.cyc,
             o_wishbone_insn_stb   = wb_insn.stb,
@@ -76,7 +76,7 @@ class Microwatt(CPU):
             i_wishbone_data_ack   = wb_data.ack,
             i_wishbone_data_stall = wb_data.cyc & ~wb_data.ack, # No burst support
 
-            o_wishbone_data_adr   = Cat(Signal(4), wb_data.adr),
+            o_wishbone_data_adr   = Cat(Signal(3), wb_data.adr),
             o_wishbone_data_dat_w = wb_data.dat_w,
             o_wishbone_data_cyc   = wb_data.cyc,
             o_wishbone_data_stb   = wb_data.stb,
diff --git a/litex/soc/cores/cpu/microwatt/crt0.S b/litex/soc/cores/cpu/microwatt/crt0.S
index 0dd6f343b..e03ac0bb4 100644
--- a/litex/soc/cores/cpu/microwatt/crt0.S
+++ b/litex/soc/cores/cpu/microwatt/crt0.S
@@ -14,8 +14,6 @@
  * limitations under the License.
  */
 
-#define STACK_TOP	0xffff4000
-
 #define FIXUP_ENDIAN						   \
 	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \
 	b     191f;	  /* Skip trampoline if endian is good	*/ \
@@ -38,24 +36,17 @@
 	oris    r,r, (e)@h;			\
 	ori     r,r, (e)@l;
 
-	.section ".head","ax"
-
 	. = 0
 .global _start
 _start:
 	FIXUP_ENDIAN
 
 	/* setup stack */
-	LOAD_IMM64(%r1, STACK_TOP - 0x100)
+	LOAD_IMM64(%r1, _fstack - 0x100)
 	LOAD_IMM64(%r12, main)
 	mtctr	%r12,
 	bctrl
-	ba	0
-
-	/* XXX: litedram init should not take exceptions, maybe we could get
-	 *      rid of these to save space, along with a core tweak to suppress
-	 *      exceptions in case they happen (just terminate ?)
-	 */
+	b .
 
 #define EXCEPTION(nr)		\
 	.=  nr;      \