From 9c801fbe50bd0b988e1be2c4b97427cbf358484d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Dec 2018 15:03:05 +0100 Subject: [PATCH] soc/cores/clock/ECP5PLL: add basic phase support --- litex/soc/cores/clock.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index aeb144540..313e25838 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -206,7 +206,7 @@ class S7IDELAYCTRL(Module): # Lattice # TODO: -# - add phase shift support +# - add proper phase support. class ECP5PLL(Module): nclkouts_max = 3 @@ -241,7 +241,6 @@ class ECP5PLL(Module): (clko_freq_min, clko_freq_max) = self.clko_freq_range assert freq >= clko_freq_min assert freq <= clko_freq_max - assert phase == 0 assert self.nclkouts < self.nclkouts_max clkout = Signal() self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) @@ -301,6 +300,6 @@ class ECP5PLL(Module): self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED" self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)] self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0 - self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = 0 + self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = p self.params["o_CLKO{}".format(n_to_l[n])] = clk self.specials += Instance("EHXPLLL", **self.params)