From 9c905830dcae7eec9f87536791186486a1912f8f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 2 Oct 2015 11:17:47 +0800 Subject: [PATCH] sdram: cleanup --- misoc/cores/lasmicon/__init__.py | 2 +- misoc/cores/lasmicon/core.py | 23 +++----- misoc/cores/lasmicon/multiplexer.py | 14 +---- misoc/cores/minicon/__init__.py | 2 +- misoc/cores/minicon/core.py | 5 -- misoc/cores/sdram_phy/gensdrphy.py | 5 +- misoc/cores/sdram_phy/k7ddrphy.py | 5 +- misoc/cores/sdram_phy/s6ddrphy.py | 22 +++---- misoc/cores/sdram_settings.py | 7 +-- misoc/integration/builder.py | 11 ++-- misoc/integration/soc_sdram.py | 90 ++++++++++------------------- misoc/targets/de0nano.py | 11 ++-- misoc/targets/kc705.py | 11 ++-- misoc/targets/minispartan6.py | 11 ++-- misoc/targets/mlabs_video.py | 10 ++-- misoc/targets/papilio_pro.py | 11 ++-- misoc/targets/pipistrello.py | 11 ++-- 17 files changed, 94 insertions(+), 157 deletions(-) diff --git a/misoc/cores/lasmicon/__init__.py b/misoc/cores/lasmicon/__init__.py index ad28bfcbf..a66d8c04d 100644 --- a/misoc/cores/lasmicon/__init__.py +++ b/misoc/cores/lasmicon/__init__.py @@ -1 +1 @@ -from misoc.cores.lasmicon.core import LASMIcon +from misoc.cores.lasmicon.core import ControllerSettings, LASMIcon diff --git a/misoc/cores/lasmicon/core.py b/misoc/cores/lasmicon/core.py index 8e2592c44..bd53825e3 100644 --- a/misoc/cores/lasmicon/core.py +++ b/misoc/cores/lasmicon/core.py @@ -6,25 +6,19 @@ from misoc.cores.lasmicon.bankmachine import * from misoc.cores.lasmicon.multiplexer import * -class LASMIconSettings: - def __init__(self, req_queue_size=8, - read_time=32, write_time=16, - l2_size=8192, - with_bandwidth=False, - with_memtest=False): +class ControllerSettings: + def __init__(self, req_queue_size=8, read_time=32, write_time=16, with_bandwidth=False): self.req_queue_size = req_queue_size self.read_time = read_time self.write_time = write_time - self.l2_size = l2_size - if with_memtest: - self.with_bandwidth = True - else: - self.with_bandwidth = with_bandwidth - self.with_memtest = with_memtest + self.with_bandwidth = with_bandwidth class LASMIcon(Module): - def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs): + def __init__(self, phy_settings, geom_settings, timing_settings, + controller_settings=None): + if controller_settings is None: + controller_settings = ControllerSettings() if phy_settings.memtype in ["SDR"]: burst_length = phy_settings.nphases*1 # command multiplication*SDR elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: @@ -53,8 +47,7 @@ class LASMIcon(Module): for i in range(2**geom_settings.bankbits)] self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings, self.bank_machines, self.refresher, - self.dfi, self.lasmic, - **kwargs) + self.dfi, self.lasmic) def get_csrs(self): return self.multiplexer.get_csrs() diff --git a/misoc/cores/lasmicon/multiplexer.py b/misoc/cores/lasmicon/multiplexer.py index 4137400f3..07d0da73d 100644 --- a/misoc/cores/lasmicon/multiplexer.py +++ b/misoc/cores/lasmicon/multiplexer.py @@ -211,20 +211,12 @@ class Multiplexer(Module, AutoCSR): ) fsm.act("REFRESH", steerer.sel[0].eq(STEER_REFRESH), + refresher.ack.eq(1), If(~refresher.req, NextState("READ")) ) fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1) - # FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog - fsm.finalize() - self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"]) - self.with_bandwidth = with_bandwidth - - def add_bandwidth(self): - self.with_bandwidth = True - - def do_finalize(self): - if self.with_bandwidth: - data_width = self.phy_settings.dfi_databits*self.phy_settings.nphases + if controller_settings.with_bandwidth: + data_width = phy_settings.dfi_databits*phy_settings.nphases self.submodules.bandwidth = Bandwidth(self.choose_req.cmd, data_width) diff --git a/misoc/cores/minicon/__init__.py b/misoc/cores/minicon/__init__.py index 5b423e41f..6fba1a1fe 100644 --- a/misoc/cores/minicon/__init__.py +++ b/misoc/cores/minicon/__init__.py @@ -1 +1 @@ -from misoc.cores.minicon.core import Minicon, MiniconSettings +from misoc.cores.minicon.core import Minicon diff --git a/misoc/cores/minicon/core.py b/misoc/cores/minicon/core.py index dbc51465a..871d087b6 100644 --- a/misoc/cores/minicon/core.py +++ b/misoc/cores/minicon/core.py @@ -60,11 +60,6 @@ class _Bank(Module): self.comb += self.hit.eq(~self.idle & (self.row == row)) -class MiniconSettings: - def __init__(self, l2_size=0): - self.l2_size = l2_size - - class Minicon(Module): def __init__(self, phy_settings, geom_settings, timing_settings): if phy_settings.memtype in ["SDR"]: diff --git a/misoc/cores/sdram_phy/gensdrphy.py b/misoc/cores/sdram_phy/gensdrphy.py index 9fc9cce7e..b704a6bdb 100644 --- a/misoc/cores/sdram_phy/gensdrphy.py +++ b/misoc/cores/sdram_phy/gensdrphy.py @@ -30,13 +30,13 @@ from misoc.cores import sdram_settings class GENSDRPHY(Module): - def __init__(self, pads, module): + def __init__(self, pads): addressbits = len(pads.a) bankbits = len(pads.ba) databits = len(pads.dq) self.settings = sdram_settings.PhySettings( - memtype=module.memtype, + memtype="SDR", dfi_databits=databits, nphases=1, rdphase=0, @@ -47,7 +47,6 @@ class GENSDRPHY(Module): read_latency=4, write_latency=0 ) - self.module = module self.dfi = Interface(addressbits, bankbits, databits) diff --git a/misoc/cores/sdram_phy/k7ddrphy.py b/misoc/cores/sdram_phy/k7ddrphy.py index cc63ad18c..bb91ef0b1 100644 --- a/misoc/cores/sdram_phy/k7ddrphy.py +++ b/misoc/cores/sdram_phy/k7ddrphy.py @@ -8,7 +8,7 @@ from misoc.cores import sdram_settings class K7DDRPHY(Module, AutoCSR): - def __init__(self, pads, module): + def __init__(self, pads): addressbits = len(pads.a) bankbits = len(pads.ba) databits = len(pads.dq) @@ -26,7 +26,7 @@ class K7DDRPHY(Module, AutoCSR): self._wdly_dqs_inc = CSR() self.settings = sdram_settings.PhySettings( - memtype=module.memtype, + memtype="DDR3", dfi_databits=2*databits, nphases=nphases, rdphase=0, @@ -38,7 +38,6 @@ class K7DDRPHY(Module, AutoCSR): read_latency=6, write_latency=2 ) - self.module = module self.dfi = Interface(addressbits, bankbits, 2*databits, nphases) diff --git a/misoc/cores/sdram_phy/s6ddrphy.py b/misoc/cores/sdram_phy/s6ddrphy.py index 71fdfa2de..decd6ada1 100644 --- a/misoc/cores/sdram_phy/s6ddrphy.py +++ b/misoc/cores/sdram_phy/s6ddrphy.py @@ -27,15 +27,15 @@ from misoc.cores import sdram_settings class S6HalfRateDDRPHY(Module): - def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment): - if module.memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]: + def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment): + if memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]: raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3") addressbits = len(pads.a) bankbits = len(pads.ba) databits = len(pads.dq) nphases = 2 - if module.memtype == "DDR3": + if memtype == "DDR3": self.settings = sdram_settings.PhySettings( memtype="DDR3", dfi_databits=2*databits, @@ -51,7 +51,7 @@ class S6HalfRateDDRPHY(Module): ) else: self.settings = sdram_settings.PhySettings( - memtype=module.memtype, + memtype=memtype, dfi_databits=2*databits, nphases=nphases, rdphase=0, @@ -63,8 +63,6 @@ class S6HalfRateDDRPHY(Module): write_latency=0 ) - self.module = module - self.dfi = Interface(addressbits, bankbits, 2*databits, nphases) self.clk4x_wr_strb = Signal() self.clk4x_rd_strb = Signal() @@ -366,7 +364,7 @@ class S6HalfRateDDRPHY(Module): wrdata_en = Signal() self.comb += wrdata_en.eq(reduce(or_, [d_dfi[p].wrdata_en for p in range(nphases)])) - if module.memtype == "DDR3": + if memtype == "DDR3": r_drive_dq = Signal(self.settings.cwl-1) sd_sdram_half += r_drive_dq.eq(Cat(wrdata_en, r_drive_dq)) self.comb += drive_dq.eq(r_drive_dq[self.settings.cwl-2]) @@ -379,7 +377,7 @@ class S6HalfRateDDRPHY(Module): r_dfi_wrdata_en = Signal(max(self.settings.cwl, self.settings.cl)) sd_sdram_half += r_dfi_wrdata_en.eq(Cat(wrdata_en_d, r_dfi_wrdata_en)) - if module.memtype == "DDR3": + if memtype == "DDR3": self.comb += drive_dqs.eq(r_dfi_wrdata_en[self.settings.cwl-1]) else: self.comb += drive_dqs.eq(r_dfi_wrdata_en[1]) @@ -399,10 +397,8 @@ class S6HalfRateDDRPHY(Module): class S6QuarterRateDDRPHY(Module): - def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment): - if module.memtype not in ["DDR3"]: - raise NotImplementedError("S6QuarterRateDDRPHY only supports DDR3") - half_rate_phy = S6HalfRateDDRPHY(pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment) + def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment): + half_rate_phy = S6HalfRateDDRPHY(pads, "DDR3", rd_bitslip, wr_bitslip, dqs_ddr_alignment) self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"}) addressbits = len(pads.a) @@ -424,8 +420,6 @@ class S6QuarterRateDDRPHY(Module): write_latency=2//2 ) - self.module = module - self.dfi = Interface(addressbits, bankbits, 2*databits, nphases) self.clk8x_wr_strb = half_rate_phy.clk4x_wr_strb self.clk8x_rd_strb = half_rate_phy.clk4x_rd_strb diff --git a/misoc/cores/sdram_settings.py b/misoc/cores/sdram_settings.py index 37a0b1de1..ce575a4ab 100644 --- a/misoc/cores/sdram_settings.py +++ b/misoc/cores/sdram_settings.py @@ -58,7 +58,7 @@ class IS42S16160(SDRAMModule): "nrows": 8192, "ncols": 512 } - # Note: timings for -7 speedgrade (add support for others speedgrades) + # Timings for -7 speedgrade timing_settings = { "tRP": 20, "tRCD": 20, @@ -68,7 +68,7 @@ class IS42S16160(SDRAMModule): "tRFC": 70 } def __init__(self, clk_freq): - SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, + SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, self.timing_settings) @@ -97,7 +97,7 @@ class AS4C16M16(SDRAMModule): "nrows": 8192, "ncols": 512 } - # Note: timings for -6 speedgrade (add support for others speedgrades) + # Timings for -6 speedgrade timing_settings = { "tRP": 18, "tRCD": 18, @@ -225,7 +225,6 @@ class MT41J128M16(SDRAMModule): "tREFI": 64*1000*1000/16384, "tRFC": 260, } - def __init__(self, clk_freq): SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings, self.timing_settings) diff --git a/misoc/integration/builder.py b/misoc/integration/builder.py index e731ef50c..44138ea30 100644 --- a/misoc/integration/builder.py +++ b/misoc/integration/builder.py @@ -2,7 +2,7 @@ import os import subprocess import struct -from misoc.integration import cpu_interface, sdram_init +from misoc.integration import cpu_interface, soc_sdram, sdram_init __all__ = ["misoc_software_packages", "misoc_directory", @@ -53,11 +53,10 @@ class Builder: flash_boot_address = getattr(self.soc, "flash_boot_address", None) csr_regions = self.soc.get_csr_regions() constants = self.soc.get_constants() - # TODO: cleanup - sdram_phy_settings = None - for sdram_phy in "sdrphy", "ddrphy": - if hasattr(self.soc, sdram_phy): - sdram_phy_settings = getattr(self.soc, sdram_phy).settings + if isinstance(self.soc, soc_sdram.SoCSDRAM): + sdram_phy_settings = self.soc._sdram_phy[0].settings + else: + sdram_phy_settings = None buildinc_dir = os.path.join(self.output_dir, "software", "include") generated_dir = os.path.join(buildinc_dir, "generated") diff --git a/misoc/integration/soc_sdram.py b/misoc/integration/soc_sdram.py index 1bc813d55..88957d33d 100644 --- a/misoc/integration/soc_sdram.py +++ b/misoc/integration/soc_sdram.py @@ -3,38 +3,28 @@ from migen.genlib.record import * from misoc.interconnect import wishbone, wishbone2lasmi, lasmi_bus from misoc.interconnect.csr import AutoCSR -from misoc.cores import sdram_tester, dfii, minicon, lasmicon +from misoc.cores import dfii, minicon, lasmicon from misoc.integration.soc_core import * -# TODO: cleanup -from misoc.cores.lasmicon.core import LASMIconSettings -from misoc.cores.minicon.core import MiniconSettings - __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"] -class SDRAMCore(Module, AutoCSR): - def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs): - # DFI +class ControllerInjector(Module, AutoCSR): + def __init__(self, phy, controller_type, geom_settings, timing_settings): self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits, phy.settings.dfi_databits, phy.settings.nphases) self.comb += Record.connect(self.dfii.master, phy.dfi) - # LASMICON - if isinstance(controller_settings, LASMIconSettings): + if controller_type == "lasmicon": self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, - timing_settings, - controller_settings, - **kwargs) + timing_settings) self.comb += Record.connect(controller.dfi, self.dfii.slave) self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic], controller.nrowbits) - - # MINICON - elif isinstance(controller_settings, MiniconSettings): + elif controller_type == "minicon": self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings) @@ -46,20 +36,15 @@ class SDRAMCore(Module, AutoCSR): class SoCSDRAM(SoCCore): csr_map = { "sdram": 8, - "l2_cache": 9, - "memtest_w": 10, - "memtest_r": 11 + "l2_cache": 9 } csr_map.update(SoCCore.csr_map) - def __init__(self, platform, clk_freq, sdram_controller_settings, - **kwargs): + def __init__(self, platform, clk_freq, l2_size=8192, **kwargs): SoCCore.__init__(self, platform, clk_freq, **kwargs) - if isinstance(sdram_controller_settings, str): - self.sdram_controller_settings = eval(sdram_controller_settings) - else: - self.sdram_controller_settings = sdram_controller_settings - self._sdram_phy_registered = False + self.l2_size = l2_size + + self._sdram_phy = [] self._wb_sdram_ifs = [] self._wb_sdram = wishbone.Interface() @@ -68,45 +53,32 @@ class SoCSDRAM(SoCCore): raise FinalizeError self._wb_sdram_ifs.append(interface) - def register_sdram_phy(self, phy): - if self._sdram_phy_registered: - raise FinalizeError - self._sdram_phy_registered = True + def register_sdram(self, phy, sdram_controller_type, geom_settings, timing_settings): + assert not self._sdram_phy + self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning - # Core - self.submodules.sdram = SDRAMCore(phy, - phy.module.geom_settings, - phy.module.timing_settings, - self.sdram_controller_settings) + self.submodules.sdram = ControllerInjector( + phy, sdram_controller_type, geom_settings, timing_settings) dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2 sdram_width = phy.settings.dfi_databits//dfi_databits_divisor - main_ram_size = 2**(phy.module.geom_settings.bankbits + - phy.module.geom_settings.rowbits + - phy.module.geom_settings.colbits)*sdram_width//8 + main_ram_size = 2**(geom_settings.bankbits + + geom_settings.rowbits + + geom_settings.colbits)*sdram_width//8 # XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories. main_ram_size = min(main_ram_size, 256*1024*1024) - l2_size = self.sdram_controller_settings.l2_size - if l2_size: - self.add_constant("L2_SIZE", l2_size) + if self.l2_size: + self.add_constant("L2_SIZE", self.l2_size) # add a Wishbone interface to the DRAM wb_sdram = wishbone.Interface() self.add_wb_sdram_if(wb_sdram) self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size) - # LASMICON frontend - if isinstance(self.sdram_controller_settings, LASMIconSettings): - if self.sdram_controller_settings.with_bandwidth: - self.sdram.controller.multiplexer.add_bandwidth() - - if self.sdram_controller_settings.with_memtest: - self.submodules.memtest_w = sdram_tester.Writer(self.sdram.crossbar.get_master()) - self.submodules.memtest_r = sdram_tester.Reader(self.sdram.crossbar.get_master()) - - if l2_size: + if sdram_controller_type == "lasmicon": + if self.l2_size: lasmim = self.sdram.crossbar.get_master() - l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw)) + l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw)) # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx and should be fixed in next releases (2015.2?). # Remove this workaround when fixed by Xilinx. @@ -117,11 +89,9 @@ class SoCSDRAM(SoCCore): else: self.submodules.l2_cache = l2_cache self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim) - - # MINICON frontend - elif isinstance(self.sdram_controller_settings, MiniconSettings): - if l2_size: - l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, self.sdram.controller.bus) + elif sdram_controller_type == "minicon": + if self.l2_size: + l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, self.sdram.controller.bus) # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx and should be fixed in next releases (2015.2?). # Remove this workaround when fixed by Xilinx. @@ -133,11 +103,13 @@ class SoCSDRAM(SoCCore): self.submodules.l2_cache = l2_cache else: self.submodules.converter = wishbone.Converter(self._wb_sdram, self.sdram.controller.bus) + else: + raise ValueError def do_finalize(self): if not self.integrated_main_ram_size: - if not self._sdram_phy_registered: - raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()") + if not self._sdram_phy: + raise FinalizeError("Need to call SDRAMSoC.register_sdram()") # arbitrate wishbone interfaces to the DRAM self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs, diff --git a/misoc/targets/de0nano.py b/misoc/targets/de0nano.py index 2e8d80e1b..f73a6d774 100755 --- a/misoc/targets/de0nano.py +++ b/misoc/targets/de0nano.py @@ -7,7 +7,6 @@ from migen.build.platforms import de0nano from misoc.cores.sdram_settings import IS42S16160 from misoc.cores.sdram_phy import GENSDRPHY -from misoc.cores.lasmicon.core import LASMIconSettings from misoc.integration.soc_sdram import * from misoc.integration.builder import * @@ -86,20 +85,20 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): - def __init__(self, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, **kwargs): platform = de0nano.Platform() SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, integrated_rom_size=0x8000, - sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform) if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), - IS42S16160(self.clk_freq)) - self.register_sdram_phy(self.sdrphy) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + sdram_module = IS42S16160(self.clk_freq) + self.register_sdram(self.sdrphy, "minicon", + sdram_module.geom_settings, sdram_module.timing_settings) def main(): parser = argparse.ArgumentParser(description="MiSoC port to the Altera DE0 Nano") diff --git a/misoc/targets/kc705.py b/misoc/targets/kc705.py index b58e69a34..3f13250e4 100755 --- a/misoc/targets/kc705.py +++ b/misoc/targets/kc705.py @@ -8,7 +8,6 @@ from migen.build.platforms import kc705 from misoc.cores.sdram_settings import MT8JTF12864 from misoc.cores.sdram_phy import k7ddrphy -from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores import spi_flash from misoc.cores.liteeth_mini.phy import LiteEthPHY from misoc.cores.liteeth_mini.mac import LiteEthMAC @@ -84,19 +83,19 @@ class BaseSoC(SoCSDRAM): } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, toolchain="ise", sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, toolchain="ise", **kwargs): platform = kc705.Platform(toolchain=toolchain) SoCSDRAM.__init__(self, platform, clk_freq=125*1000000, cpu_reset_address=0xaf0000, - sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform) if not self.integrated_main_ram_size: - self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), - MT8JTF12864(self.clk_freq)) - self.register_sdram_phy(self.ddrphy) + self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram")) + sdram_module = MT8JTF12864(self.clk_freq) + self.register_sdram(self.ddrphy, "lasmicon", + sdram_module.geom_settings, sdram_module.timing_settings) if not self.integrated_rom_size: spiflash_pads = platform.request("spiflash") diff --git a/misoc/targets/minispartan6.py b/misoc/targets/minispartan6.py index 040ead10e..72f5e0c8d 100755 --- a/misoc/targets/minispartan6.py +++ b/misoc/targets/minispartan6.py @@ -9,7 +9,6 @@ from migen.build.platforms import minispartan6 from misoc.cores.sdram_settings import AS4C16M16 from misoc.cores.sdram_phy import GENSDRPHY -from misoc.cores.lasmicon.core import LASMIconSettings from misoc.integration.soc_sdram import * from misoc.integration.builder import * @@ -66,20 +65,20 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): - def __init__(self, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, **kwargs): clk_freq = 80*1000000 platform = minispartan6.Platform() SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, - sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), - AS4C16M16(clk_freq)) - self.register_sdram_phy(self.sdrphy) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + sdram_module = AS4C16M16(clk_freq) + self.register_sdram(self.sdrphy, "minicon", + sdram_module.geom_settings, sdram_module.timing_settings) def main(): diff --git a/misoc/targets/mlabs_video.py b/misoc/targets/mlabs_video.py index 8f2f86012..670c7fc4a 100755 --- a/misoc/targets/mlabs_video.py +++ b/misoc/targets/mlabs_video.py @@ -11,7 +11,6 @@ from migen.build.platforms import mixxeo, m1 from misoc.cores.sdram_settings import MT46V32M16 from misoc.cores.sdram_phy import S6HalfRateDDRPHY -from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores import nor_flash_16 # TODO: from misoc.cores import framebuffer from misoc.cores import gpio @@ -75,7 +74,7 @@ class _MXClockPads: class BaseSoC(SoCSDRAM): - def __init__(self, platform_name="mixxeo", sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, platform_name="mixxeo", **kwargs): if platform_name == "mixxeo": platform = mixxeo.Platform() elif platform_name == "m1": @@ -85,18 +84,19 @@ class BaseSoC(SoCSDRAM): SoCSDRAM.__init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000000, cpu_reset_address=0x00180000, - sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq) if not self.integrated_main_ram_size: + sdram_module = MT46V32M16(self.clk_freq) self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"), - MT46V32M16(self.clk_freq), + sdram_module.memtype, rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") - self.register_sdram_phy(self.ddrphy) + self.register_sdram(self.ddrphy, "lasmicon", + sdram_module.geom_settings, sdram_module.timing_settings) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb) diff --git a/misoc/targets/papilio_pro.py b/misoc/targets/papilio_pro.py index f41a4d3b1..9710553f7 100755 --- a/misoc/targets/papilio_pro.py +++ b/misoc/targets/papilio_pro.py @@ -9,7 +9,6 @@ from migen.build.platforms import papilio_pro from misoc.cores.sdram_settings import MT48LC4M16 from misoc.cores.sdram_phy import GENSDRPHY -from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores import spi_flash from misoc.integration.soc_sdram import * from misoc.integration.builder import * @@ -72,20 +71,20 @@ class BaseSoC(SoCSDRAM): } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, sdram_controller_settings=LASMIconSettings(), **kwargs): + def __init__(self, **kwargs): platform = papilio_pro.Platform() clk_freq = 80*1000000 SoCSDRAM.__init__(self, platform, clk_freq, cpu_reset_address=0x60000, - sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), - MT48LC4M16(clk_freq)) - self.register_sdram_phy(self.sdrphy) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + sdram_module = MT48LC4M16(clk_freq) + self.register_sdram(self.sdrphy, "minicon", + sdram_module.geom_settings, sdram_module.timing_settings) if not self.integrated_rom_size: self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash2x"), diff --git a/misoc/targets/pipistrello.py b/misoc/targets/pipistrello.py index 1a4f50d0a..36abd688d 100755 --- a/misoc/targets/pipistrello.py +++ b/misoc/targets/pipistrello.py @@ -9,7 +9,6 @@ from migen.build.platforms import pipistrello from misoc.cores.sdram_settings import MT46H32M16 from misoc.cores.sdram_phy import S6HalfRateDDRPHY -from misoc.cores.lasmicon.core import LASMIconSettings from misoc.cores import spi_flash from misoc.integration.soc_sdram import * from misoc.integration.builder import * @@ -101,19 +100,18 @@ class BaseSoC(SoCSDRAM): } csr_map.update(SoCSDRAM.csr_map) - def __init__(self, sdram_controller_settings=LASMIconSettings(), - clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs): + def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs): platform = pipistrello.Platform() SoCSDRAM.__init__(self, platform, clk_freq, cpu_reset_address=0x170000, # 1.5 MB - sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) if not self.integrated_main_ram_size: + sdram_module = MT46H32M16(self.clk_freq) self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"), - MT46H32M16(self.clk_freq), + sdram_module.memtype, rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") @@ -121,7 +119,8 @@ class BaseSoC(SoCSDRAM): self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] - self.register_sdram_phy(self.ddrphy) + self.register_sdram(self.ddrphy, "minicon", + sdram_module.geom_settings, sdram_module.timing_settings) if not self.integrated_rom_size: self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash4x"),