diff --git a/litex/build/sim/core/libdylib.c b/litex/build/sim/core/libdylib.c
index ba8cdb6a0..aaf082288 100644
--- a/litex/build/sim/core/libdylib.c
+++ b/litex/build/sim/core/libdylib.c
@@ -39,7 +39,7 @@ static void set_last_error(const char *s)
     if (!s)
         s = "NULL error";
     last_err_set = 1;
-    strncpy(last_err, s, ERR_MAX_SIZE);
+    strncpy(last_err, s, ERR_MAX_SIZE-1);
 }
 
 static dylib_ref dylib_ref_alloc (void *handle, const char *path)
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 11e08a3fc..c8cdc1794 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -384,7 +384,7 @@ class SoCCore(Module):
 
 def soc_core_args(parser):
     parser.add_argument("--cpu-type", default=None,
-                        help="select CPU: lm32, mor1kx, picorv32, vexriscv, minerva")
+                        help="select CPU: lm32, or1k, picorv32, vexriscv, minerva")
     parser.add_argument("--cpu-variant", default=None,
                         help="select CPU variant")
     parser.add_argument("--integrated-rom-size", default=None, type=int,
diff --git a/litex/soc/software/libbase/exception.c b/litex/soc/software/libbase/exception.c
index b758e58ee..09b26399a 100644
--- a/litex/soc/software/libbase/exception.c
+++ b/litex/soc/software/libbase/exception.c
@@ -25,7 +25,7 @@ static void emerg_printf(const char *fmt, ...)
 	}
 }
 
-static char emerg_getc()
+static char emerg_getc(void)
 {
 	while(uart_rxempty_read());
 	char c = uart_rxtx_read();