From 9d5931c969810a236de2a2713cfd5e509839d097 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 19 Nov 2013 23:15:42 +0100 Subject: [PATCH] platforms/mixxeo: update DVI input timing constraints --- mibuild/platforms/mixxeo.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index c797b09e7..12b242fb8 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -185,7 +185,7 @@ TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; try: self.add_platform_command(""" NET "{dviclk}" TNM_NET = "GRP"""+si+""""; -TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 26.7 ns HIGH 50%; +TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 12.00 ns HIGH 50%; """, dviclk=self.lookup_request("dvi_in", i).clk_p) except ConstraintError: pass