diff --git a/litex/soc/cores/cpu/femtorv/core.py b/litex/soc/cores/cpu/femtorv/core.py
index 62b84bec9..0ee9a01c4 100644
--- a/litex/soc/cores/cpu/femtorv/core.py
+++ b/litex/soc/cores/cpu/femtorv/core.py
@@ -147,18 +147,6 @@ class FemtoRV(CPU):
         self.comb += mbus.rdata.eq(mbus_rdata)             # Latched value.
         self.comb += If(latch, mbus.rdata.eq(idbus.dat_r)) # Immediate value.
 
-        # Main Ram accesses debug.
-        if False:
-            self.sync += If(mbus.addr[28:32] == 0x4, # Only Display Main Ram accesses.
-                If(idbus.stb & idbus.ack,
-                    If(idbus.we,
-                        Display("Write: Addr 0x%08x : Data 0x%08x, Sel: 0x%x", idbus.adr, idbus.dat_w, idbus.sel)
-                    ).Else(
-                        Display("Read:  Addr 0x%08x : Data 0x%08x", idbus.adr, idbus.dat_r)
-                    )
-                )
-            )
-
         # Add Verilog sources.
         # --------------------
         self.add_sources(platform, variant)
diff --git a/litex/soc/cores/cpu/firev/core.py b/litex/soc/cores/cpu/firev/core.py
index 58087fc32..bf0bbcf02 100644
--- a/litex/soc/cores/cpu/firev/core.py
+++ b/litex/soc/cores/cpu/firev/core.py
@@ -120,16 +120,6 @@ class firev(CPU):
             mbus.in_ram_data_out.eq(idbus.dat_r),
             mbus.in_ram_done.eq(idbus.ack),
         ]
- 
-        # Main Ram accesses debug.
-        if False:
-            self.sync += If(idbus.stb & idbus.ack,
-                    If(idbus.we,
-                        Display("Write: Addr 0x%08x : Data 0x%08x, Sel: 0x%x", idbus.adr, idbus.dat_w, idbus.sel)
-                    ).Else(
-                        Display("Read:  Addr 0x%08x : Data 0x%08x", idbus.adr, idbus.dat_r)
-                    )
-                )
 
         # Add Verilog sources.
         # --------------------