diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 6afbd1fe5..41fba33c0 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -22,23 +22,25 @@ from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 # Variants -----------------------------------------------------------------------------------------
 
 CPU_VARIANTS = {
-    "minimal":          "VexRiscv_Min",
-    "minimal+debug":    "VexRiscv_MinDebug",
-    "lite":             "VexRiscv_Lite",
-    "lite+debug":       "VexRiscv_LiteDebug",
-    "standard":         "VexRiscv",
-    "standard+debug":   "VexRiscv_Debug",
-    "imac":             "VexRiscv_IMAC",
-    "imac+debug":       "VexRiscv_IMACDebug",
-    "full":             "VexRiscv_Full",
-    "full+cfu":         "VexRiscv_FullCfu",
-    "full+debug":       "VexRiscv_FullDebug",
-    "full+cfu+debug":   "VexRiscv_FullCfuDebug",
-    "linux":            "VexRiscv_Linux",
-    "linux+debug":      "VexRiscv_LinuxDebug",
-    "linux+no-dsp":     "VexRiscv_LinuxNoDspFmax",
-    "secure":           "VexRiscv_Secure",
-    "secure+debug":     "VexRiscv_SecureDebug",
+    "minimal":            "VexRiscv_Min",
+    "minimal+debug":      "VexRiscv_MinDebug",
+    "minimal+debug+hwbp": "VexRiscv_MinDebugHwBP",
+    "lite":               "VexRiscv_Lite",
+    "lite+debug":         "VexRiscv_LiteDebug",
+    "lite+debug+hwbp":    "VexRiscv_LiteDebugHwBP",
+    "standard":           "VexRiscv",
+    "standard+debug":     "VexRiscv_Debug",
+    "imac":               "VexRiscv_IMAC",
+    "imac+debug":         "VexRiscv_IMACDebug",
+    "full":               "VexRiscv_Full",
+    "full+cfu":           "VexRiscv_FullCfu",
+    "full+debug":         "VexRiscv_FullDebug",
+    "full+cfu+debug":     "VexRiscv_FullCfuDebug",
+    "linux":              "VexRiscv_Linux",
+    "linux+debug":        "VexRiscv_LinuxDebug",
+    "linux+no-dsp":       "VexRiscv_LinuxNoDspFmax",
+    "secure":             "VexRiscv_Secure",
+    "secure+debug":       "VexRiscv_SecureDebug",
 }
 
 # GCC Flags ----------------------------------------------------------------------------------------