From 9e14b1b05188d0130b35299408ccf8915f8e46c3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 19 Dec 2014 01:35:18 +0100 Subject: [PATCH] use new implicit submodules collection and Pipeline --- lib/sata/__init__.py | 6 +++--- lib/sata/command/__init__.py | 6 +++--- lib/sata/common.py | 1 + lib/sata/link/__init__.py | 6 +++--- lib/sata/link/crc.py | 2 +- lib/sata/link/scrambler.py | 2 +- lib/sata/phy/__init__.py | 10 +++++----- lib/sata/phy/datapath.py | 4 ++-- lib/sata/test/bist_tb.py | 16 +++++++++------- lib/sata/test/command_tb.py | 33 +++++++++++++++++---------------- lib/sata/test/crc_tb.py | 2 +- lib/sata/test/hdd.py | 12 ++++++------ lib/sata/test/link_tb.py | 2 -- lib/sata/test/scrambler_tb.py | 2 +- lib/sata/transport/__init__.py | 4 ++-- targets/test.py | 32 ++++++++++++++++---------------- 16 files changed, 71 insertions(+), 69 deletions(-) diff --git a/lib/sata/__init__.py b/lib/sata/__init__.py index ddb481b6a..69a12bf6e 100644 --- a/lib/sata/__init__.py +++ b/lib/sata/__init__.py @@ -5,8 +5,8 @@ from lib.sata.command import SATACommand class SATACON(Module): def __init__(self, phy, sector_size=512, max_count=8): - self.submodules.link = SATALink(phy) - self.submodules.transport = SATATransport(self.link) - self.submodules.command = SATACommand(self.transport, sector_size=sector_size, max_count=max_count) + self.link = SATALink(phy) + self.transport = SATATransport(self.link) + self.command = SATACommand(self.transport, sector_size=sector_size, max_count=max_count) self.sink, self.source = self.command.sink, self.command.source diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py index f3cd5623d..cc9fc1d20 100644 --- a/lib/sata/command/__init__.py +++ b/lib/sata/command/__init__.py @@ -119,7 +119,7 @@ class SATACommandRX(Module): ### cmd_fifo = SyncFIFO(command_rx_cmd_description(32), 2) # Note: ideally depth=1 - data_fifo = InsertReset(FIFO(command_rx_data_description(32), sector_size*max_count//4, buffered=True)) + data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), sector_size*max_count//4, buffered=True)) self.submodules += cmd_fifo, data_fifo def test_type(name): @@ -271,8 +271,8 @@ class SATACommand(Module): def __init__(self, transport, sector_size=512, max_count=4): if max_count*sector_size > 8192: raise ValueError("sector_size * max_count must be <= 8192") - self.submodules.tx = SATACommandTX(transport, sector_size) - self.submodules.rx = SATACommandRX(transport, sector_size, max_count) + self.tx = SATACommandTX(transport, sector_size) + self.rx = SATACommandRX(transport, sector_size, max_count) self.comb += [ self.rx.to_tx.connect(self.tx.from_rx), self.tx.to_rx.connect(self.rx.from_tx) diff --git a/lib/sata/common.py b/lib/sata/common.py index 404bddb58..2bd5c0900 100644 --- a/lib/sata/common.py +++ b/lib/sata/common.py @@ -4,6 +4,7 @@ from migen.genlib.fsm import * from migen.genlib.record import * from migen.flow.actor import * from migen.actorlib.fifo import * +from migen.actorlib.structuring import Pipeline # PHY / Link Layers primitives = { diff --git a/lib/sata/link/__init__.py b/lib/sata/link/__init__.py index 44fdfe016..4182643d7 100644 --- a/lib/sata/link/__init__.py +++ b/lib/sata/link/__init__.py @@ -147,7 +147,7 @@ class SATALinkRX(Module): ) # small fifo to manage HOLD - self.submodules.fifo = SyncFIFO(link_description(32), 32) + self.fifo = SyncFIFO(link_description(32), 32) # graph self.sync += \ @@ -210,7 +210,7 @@ class SATALinkRX(Module): class SATALink(Module): def __init__(self, phy): - self.submodules.tx = SATALinkTX(phy) - self.submodules.rx = SATALinkRX(phy) + self.tx = SATALinkTX(phy) + self.rx = SATALinkRX(phy) self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx) self.sink, self.source = self.tx.sink, self.rx.source diff --git a/lib/sata/link/crc.py b/lib/sata/link/crc.py index a702a2106..72157ce53 100644 --- a/lib/sata/link/crc.py +++ b/lib/sata/link/crc.py @@ -95,7 +95,7 @@ class SATACRC(Module): ### - self.submodules.engine = CRCEngine(self.width, self.polynom) + self.engine = CRCEngine(self.width, self.polynom) reg_i = Signal(self.width, reset=self.init) self.sync += reg_i.eq(self.engine.next) self.comb += [ diff --git a/lib/sata/link/scrambler.py b/lib/sata/link/scrambler.py index 446faeeb8..d2b473f86 100644 --- a/lib/sata/link/scrambler.py +++ b/lib/sata/link/scrambler.py @@ -75,7 +75,7 @@ class SATAScrambler(Module): ### - self.submodules.scrambler = Scrambler() + self.scrambler = Scrambler() self.comb += [ self.scrambler.ce.eq(sink.stb & sink.ack), Record.connect(sink, source), diff --git a/lib/sata/phy/__init__.py b/lib/sata/phy/__init__.py index ec6d5e465..37ad32fdc 100644 --- a/lib/sata/phy/__init__.py +++ b/lib/sata/phy/__init__.py @@ -8,17 +8,17 @@ class SATAPHY(Module): if device_family == "k7": from lib.sata.phy.k7.trx import K7SATAPHYTRX from lib.sata.phy.k7.crg import K7SATAPHYCRG - self.submodules.trx = K7SATAPHYTRX(pads, speed) - self.submodules.crg = K7SATAPHYCRG(pads, self.trx, clk_freq, speed) + self.trx = K7SATAPHYTRX(pads, speed) + self.crg = K7SATAPHYCRG(pads, self.trx, clk_freq, speed) else: raise NotImplementedError(device_family + "device family not implemented") # Control if host: - self.submodules.ctrl = SATAPHYHostCtrl(self.trx, self.crg, clk_freq) + self.ctrl = SATAPHYHostCtrl(self.trx, self.crg, clk_freq) else: - self.submodules.ctrl = SATAPHYDeviceCtrl(self.trx, self.crg, clk_freq) + self.ctrl = SATAPHYDeviceCtrl(self.trx, self.crg, clk_freq) # Datapath - self.submodules.datapath = SATAPHYDatapath(self.trx, self.ctrl) + self.datapath = SATAPHYDatapath(self.trx, self.ctrl) self.sink, self.source = self.datapath.sink, self.datapath.source diff --git a/lib/sata/phy/datapath.py b/lib/sata/phy/datapath.py index 34149a676..6da4693f9 100644 --- a/lib/sata/phy/datapath.py +++ b/lib/sata/phy/datapath.py @@ -58,7 +58,7 @@ class SATAPHYDatapathRX(Module): # due to the convertion ratio of 2, sys_clk need to be > sata_rx/2 # source destination is always able to accept data (ack always 1) fifo = AsyncFIFO(phy_description(32), 4) - self.submodules.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"}) + self.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"}) self.comb += [ fifo.sink.stb.eq(valid), fifo.sink.data.eq(data), @@ -80,7 +80,7 @@ class SATAPHYDatapathTX(Module): # requirements: # source destination is always able to accept data (ack always 1) fifo = AsyncFIFO(phy_description(32), 4) - self.submodules.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"}) + self.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"}) self.comb += Record.connect(self.sink, fifo.sink) # 32 to 16 diff --git a/lib/sata/test/bist_tb.py b/lib/sata/test/bist_tb.py index dd17fc2ec..77e45908e 100644 --- a/lib/sata/test/bist_tb.py +++ b/lib/sata/test/bist_tb.py @@ -7,16 +7,18 @@ from lib.sata.test.common import * class TB(Module): def __init__(self): - self.submodules.hdd = HDD( + self.hdd = HDD( link_debug=False, link_random_level=0, transport_debug=False, transport_loopback=False, hdd_debug=True) - self.submodules.controller = SATACON(self.hdd.phy) - self.submodules.bist = SATABIST() - self.comb += [ - self.bist.source.connect(self.controller.sink), - self.controller.source.connect(self.bist.sink) - ] + self.controller = SATACON(self.hdd.phy) + self.bist = SATABIST() + + self.pipeline = Pipeline( + self.bist, + self.controller, + self.bist + ) def gen_simulation(self, selfp): hdd = self.hdd diff --git a/lib/sata/test/command_tb.py b/lib/sata/test/command_tb.py index cd1e073ec..fd6c3a1ee 100644 --- a/lib/sata/test/command_tb.py +++ b/lib/sata/test/command_tb.py @@ -61,26 +61,27 @@ class CommandLogger(PacketLogger): class TB(Module): def __init__(self): - self.submodules.hdd = HDD( + self.hdd = HDD( link_debug=False, link_random_level=50, transport_debug=False, transport_loopback=False, hdd_debug=True) - self.submodules.link = SATALink(self.hdd.phy) - self.submodules.transport = SATATransport(self.link) - self.submodules.command = SATACommand(self.transport) + self.link = SATALink(self.hdd.phy) + self.transport = SATATransport(self.link) + self.command = SATACommand(self.transport) - self.submodules.streamer = CommandStreamer() - streamer_ack_randomizer = AckRandomizer(command_tx_description(32), level=50) - self.submodules += streamer_ack_randomizer - self.submodules.logger = CommandLogger() - logger_ack_randomizer = AckRandomizer(command_rx_description(32), level=50) - self.submodules += logger_ack_randomizer - self.comb += [ - Record.connect(self.streamer.source, streamer_ack_randomizer.sink), - Record.connect(streamer_ack_randomizer.source, self.command.sink), - Record.connect(self.command.source, logger_ack_randomizer.sink), - Record.connect(logger_ack_randomizer.source, self.logger.sink) - ] + self.streamer = CommandStreamer() + self.streamer_randomizer = Randomizer(command_tx_description(32), level=50) + + self.logger = CommandLogger() + self.logger_randomizer = Randomizer(command_rx_description(32), level=50) + + self.pipeline = Pipeline( + self.streamer, + self.streamer_randomizer, + self.command, + self.logger_randomizer, + self.logger + ) def gen_simulation(self, selfp): hdd = self.hdd diff --git a/lib/sata/test/crc_tb.py b/lib/sata/test/crc_tb.py index 4fb47fffd..2b974fbb9 100644 --- a/lib/sata/test/crc_tb.py +++ b/lib/sata/test/crc_tb.py @@ -7,7 +7,7 @@ from lib.sata.test.common import * class TB(Module): def __init__(self, length, random): - self.submodules.crc = SATACRC() + self.crc = SATACRC() self.length = length self.random = random diff --git a/lib/sata/test/hdd.py b/lib/sata/test/hdd.py index 371d4c1a7..33652fceb 100644 --- a/lib/sata/test/hdd.py +++ b/lib/sata/test/hdd.py @@ -56,8 +56,8 @@ class PHYSink(Module): class PHYLayer(Module): def __init__(self): - self.submodules.rx = PHYSink() - self.submodules.tx = PHYSource() + self.rx = PHYSink() + self.tx = PHYSource() self.source = self.tx.source self.sink = self.rx.sink @@ -440,10 +440,10 @@ class HDD(Module): hdd_debug=False, hdd_sector_size=512, ): ### - self.submodules.phy = PHYLayer() - self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level) - self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback) - self.submodules.command = CommandLayer(self.transport) + self.phy = PHYLayer() + self.link = LinkLayer(self.phy, link_debug, link_random_level) + self.transport = TransportLayer(self.link, transport_debug, transport_loopback) + self.command = CommandLayer(self.transport) self.command.set_hdd(self) diff --git a/lib/sata/test/link_tb.py b/lib/sata/test/link_tb.py index 778b171c9..4c8e689d3 100644 --- a/lib/sata/test/link_tb.py +++ b/lib/sata/test/link_tb.py @@ -4,8 +4,6 @@ from lib.sata.link import SATALink from lib.sata.test.common import * from lib.sata.test.hdd import * -from migen.actorlib.structuring import * - class LinkStreamer(PacketStreamer): def __init__(self): PacketStreamer.__init__(self, link_description(32), LinkTXPacket) diff --git a/lib/sata/test/scrambler_tb.py b/lib/sata/test/scrambler_tb.py index 42fdf699a..69d7b63e0 100644 --- a/lib/sata/test/scrambler_tb.py +++ b/lib/sata/test/scrambler_tb.py @@ -7,7 +7,7 @@ from lib.sata.test.common import * class TB(Module): def __init__(self, length): - self.submodules.scrambler = InsertReset(Scrambler()) + self.scrambler = InsertReset(Scrambler()) self.length = length def get_c_values(self, length): diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py index dd0e4f933..abb07cc49 100644 --- a/lib/sata/transport/__init__.py +++ b/lib/sata/transport/__init__.py @@ -231,6 +231,6 @@ class SATATransportRX(Module): class SATATransport(Module): def __init__(self, link): - self.submodules.tx = SATATransportTX(link) - self.submodules.rx = SATATransportRX(link) + self.tx = SATATransportTX(link) + self.rx = SATATransportRX(link) self.sink, self.source = self.tx.sink, self.rx.source diff --git a/targets/test.py b/targets/test.py index 6ea4defc6..431fce2e2 100644 --- a/targets/test.py +++ b/targets/test.py @@ -60,17 +60,17 @@ class UART2WB(Module): interrupt_map = {} cpu_type = None def __init__(self, platform, clk_freq): - self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq) + self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq) # CSR bridge 0x00000000 (shadow @0x00000000) - self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) + self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) self._wb_masters = [self.uart2wb.wishbone] self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory) # CSR - self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0) + self.identifier = identifier.Identifier(0, int(clk_freq), 0) def add_wb_master(self, wbm): if self.finalized: @@ -90,14 +90,14 @@ class UART2WB(Module): def do_finalize(self): # Wishbone - self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, + self.wishbonecon = wishbone.InterconnectShared(self._wb_masters, self._wb_slaves, register=True) # CSR - self.submodules.csrbankarray = csrgen.BankArray(self, + self.csrbankarray = csrgen.BankArray(self, lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], data_width=self.csr_data_width) - self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) + self.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: @@ -109,15 +109,15 @@ class SimDesign(UART2WB): def __init__(self, platform, export_mila=False): clk_freq = 200*1000000 UART2WB.__init__(self, platform, clk_freq) - self.submodules.crg = _CRG(platform) + self.crg = _CRG(platform) - self.submodules.sata_phy_host = SATAPHY(platform.request("sata_host"), clk_freq, host=True) + self.sata_phy_host = SATAPHY(platform.request("sata_host"), clk_freq, host=True) self.comb += [ self.sata_phy_host.sink.stb.eq(1), self.sata_phy_host.sink.data.eq(primitives["SYNC"]), self.sata_phy_host.sink.charisk.eq(0b0001) ] - self.submodules.sata_phy_device = SATAPHY(platform.request("sata_device"), clk_freq, host=False) + self.sata_phy_device = SATAPHY(platform.request("sata_device"), clk_freq, host=False) self.comb += [ self.sata_phy_device.sink.stb.eq(1), self.sata_phy_device.sink.data.eq(primitives["SYNC"]), @@ -155,8 +155,8 @@ class VeryBasicPHYStim(Module, AutoCSR): self._tx_primitive = CSRStorage(32) self._rx_primitive = CSRStatus(32) - self.submodules.cont_inserter = SATACONTInserter(phy_description(32)) - self.submodules.cont_remover = SATACONTRemover(phy_description(32)) + self.cont_inserter = SATACONTInserter(phy_description(32)) + self.cont_remover = SATACONTRemover(phy_description(32)) self.comb += [ self.cont_inserter.source.connect(phy.sink), phy.source.connect(self.cont_remover.sink) @@ -185,12 +185,12 @@ class TestDesign(UART2WB, AutoCSR): def __init__(self, platform, mila=True, export_mila=False): clk_freq = 200*1000000 UART2WB.__init__(self, platform, clk_freq) - self.submodules.crg = _CRG(platform) + self.crg = _CRG(platform) - self.submodules.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA1") - self.submodules.stim = VeryBasicPHYStim(self.sata_phy) + self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA1") + self.stim = VeryBasicPHYStim(self.sata_phy) - self.submodules.clock_leds = ClockLeds(platform) + self.clock_leds = ClockLeds(platform) if mila: import os @@ -231,7 +231,7 @@ class TestDesign(UART2WB, AutoCSR): self.comb += platform.request("user_led", 2).eq(crg.ready) self.comb += platform.request("user_led", 3).eq(ctrl.ready) - self.submodules.mila = MiLa(depth=512, dat=Cat(*debug)) + self.mila = MiLa(depth=512, dat=Cat(*debug)) self.mila.add_port(Term) if export_mila: