diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 1c09a17e1..e4695b855 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -815,7 +815,7 @@ class SoC(Module):
             bus_csr       = csr_bus.Interface(
             address_width = self.csr.address_width,
             data_width    = self.csr.data_width),
-            register = register)
+            register      = register)
         csr_size   = 2**(self.csr.address_width + 2)
         csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
         bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_'))
diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 098b81f52..93a1e6bdd 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -732,7 +732,8 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=
     return fsm, comb
 
 class AXILite2CSR(Module):
-    def __init__(self, axi_lite=None, bus_csr=None):
+    def __init__(self, axi_lite=None, bus_csr=None, register=False):
+        # TODO: unused register argument
         if axi_lite is None:
             axi_lite = AXILiteInterface()
         if bus_csr is None: