diff --git a/verilog/mxcrg/mxcrg.v b/misoclib/mxcrg/mxcrg.v
similarity index 100%
rename from verilog/mxcrg/mxcrg.v
rename to misoclib/mxcrg/mxcrg.v
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 989a16669..9ca4e8829 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -68,7 +68,7 @@ INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
 
 PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
 """)
-		platform.add_source_dir(os.path.join("verilog", "mxcrg"))
+		platform.add_source_dir(os.path.join("misoclib", "mxcrg"))
 
 class MiniSoC(BaseSoC):
 	csr_map = {