From 9ebb8f80225d7280074a000ca1a25452fc0fdc17 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Feb 2015 10:22:17 +0100 Subject: [PATCH] remove verilog and move mxcrg.v to misoclib/mxcrg --- {verilog => misoclib}/mxcrg/mxcrg.v | 0 targets/mlabs_video.py | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename {verilog => misoclib}/mxcrg/mxcrg.v (100%) diff --git a/verilog/mxcrg/mxcrg.v b/misoclib/mxcrg/mxcrg.v similarity index 100% rename from verilog/mxcrg/mxcrg.v rename to misoclib/mxcrg/mxcrg.v diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 989a16669..9ca4e8829 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -68,7 +68,7 @@ INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE; """) - platform.add_source_dir(os.path.join("verilog", "mxcrg")) + platform.add_source_dir(os.path.join("misoclib", "mxcrg")) class MiniSoC(BaseSoC): csr_map = {