diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 5973ba372..842ed764e 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -395,7 +395,7 @@ def _print_module(f, ios, name, ns, attr_translate):
             sig.direction = "inout"
             r += "\tinout  wire " + _print_signal(ns, sig)
         elif sig in targets:
-            sig.direction = "output      "
+            sig.direction = "output"
             if sig in wires:
                 r += "\toutput wire " + _print_signal(ns, sig)
             else: