From e9613499eaa40e93bb8b07f64009e22b1dfe392d Mon Sep 17 00:00:00 2001 From: Chris Keilbart Date: Mon, 4 Nov 2024 12:01:29 -0800 Subject: [PATCH 1/3] Fix SOC region range check --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index d91f7a288..0fbc544f2 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -318,7 +318,7 @@ class SoCBusHandler(LiteXModule): is_in = True if not (region.origin >= container.origin): is_in = False - if not ((region.origin + region.size) < (container.origin + container.size)): + if not ((region.origin + region.size) <= (container.origin + container.size)): is_in = False return is_in From 2b3913982cde96c6ce13d1f58b5261d9038235ad Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 6 Nov 2024 21:49:39 +0100 Subject: [PATCH 2/3] soc/cores/cpu/urv: Add InstructionBusToWishbone and use it. --- litex/soc/cores/cpu/urv/core.py | 70 +++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 30 deletions(-) diff --git a/litex/soc/cores/cpu/urv/core.py b/litex/soc/cores/cpu/urv/core.py index 2ad030733..161716117 100644 --- a/litex/soc/cores/cpu/urv/core.py +++ b/litex/soc/cores/cpu/urv/core.py @@ -34,7 +34,38 @@ GCC_FLAGS = { "standard": "-march=rv32i2p0_m -mabi=ilp32", } -# uRV ------------------------------------------------------------------------------------------ +# uRV Instruction Bus To Wishbone ------------------------------------------------------------------ + +instruction_bus_layout = [ + ("addr", 32), + ("rd", 1), + ("data", 32), + ("valid", 1) +] + +class InstructionBusToWishbone(LiteXModule): + def __init__(self, ibus, wb_ibus): + self.fsm = fsm = FSM(reset_state="IDLE") + fsm.act("IDLE", + If(ibus.rd, + NextValue(ibus.valid, 0), + NextState("READ") + ) + ) + fsm.act("READ", + wb_ibus.stb.eq(1), + wb_ibus.cyc.eq(1), + wb_ibus.we.eq(0), + wb_ibus.adr.eq(ibus.addr), + wb_ibus.sel.eq(0b1111), + If(wb_ibus.ack, + NextValue(ibus.valid, 1), + NextValue(ibus.data, wb_ibus.dat_r), + NextState("IDLE") + ) + ) + +# uRV ---------------------------------------------------------------------------------------------- class uRV(CPU): category = "softcore" @@ -68,10 +99,7 @@ class uRV(CPU): # uRV Signals. # ------------ - im_addr = Signal(32) - im_rd = Signal() - im_data = Signal(32) - im_valid = Signal() + im_bus = Record(instruction_bus_layout) dm_addr = Signal(32) dm_data_s = Signal(32) @@ -100,10 +128,10 @@ class uRV(CPU): i_rst_i = ResetSignal("sys") | self.reset, # Instruction Mem Bus. - o_im_addr_o = im_addr, - o_im_rd_o = im_rd, - i_im_data_i = im_data, - i_im_valid_i = im_valid, + o_im_addr_o = im_bus.addr, + o_im_rd_o = im_bus.rd, + i_im_data_i = im_bus.data, + i_im_valid_i = im_bus.valid, # Data Mem Bus. o_dm_addr_o = dm_addr, @@ -117,27 +145,9 @@ class uRV(CPU): i_dm_store_done_i = dm_store_done, ) - # uRV Instruction Bus. - # -------------------- - self.i_fsm = i_fsm = FSM(reset_state="IDLE") - i_fsm.act("IDLE", - If(im_rd, - NextValue(im_valid, 0), - NextState("READ") - ) - ) - i_fsm.act("READ", - ibus.stb.eq(1), - ibus.cyc.eq(1), - ibus.we.eq(0), - ibus.adr.eq(im_addr), - ibus.sel.eq(0b1111), - If(ibus.ack, - NextValue(im_valid, 1), - NextValue(im_data, ibus.dat_r), - NextState("IDLE") - ) - ) + # uRV Bus Adaptation. + # ------------------- + self.submodules += InstructionBusToWishbone(im_bus, ibus) # uRV Data Bus. # ------------- From de9d3ab3143c97d3bbebcfd3cc1a545e27fe3e5d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 6 Nov 2024 21:59:11 +0100 Subject: [PATCH 3/3] soc/cores/cpu/urv: Add DataBusToWishbone and use it. --- litex/soc/cores/cpu/urv/core.py | 145 +++++++++++++++++--------------- 1 file changed, 76 insertions(+), 69 deletions(-) diff --git a/litex/soc/cores/cpu/urv/core.py b/litex/soc/cores/cpu/urv/core.py index 161716117..f3564e662 100644 --- a/litex/soc/cores/cpu/urv/core.py +++ b/litex/soc/cores/cpu/urv/core.py @@ -65,6 +65,70 @@ class InstructionBusToWishbone(LiteXModule): ) ) +# uRV Data Bus To Wishbone ------------------------------------------------------------------------- + +data_bus_layout = [ + ("addr", 32), + ("data_s", 32), + ("data_l", 32), + ("sel", 4), + ("store", 1), + ("load", 1), + ("load_done", 1), + ("store_done", 1) +] + +class DataBusToWishbone(LiteXModule): + def __init__(self, dbus, wb_dbus): + self.fifo = fifo = stream.SyncFIFO( + layout=[("addr", 32), ("we", 1), ("data", 32), ("sel", 4)], + depth=16, + ) + self.comb += [ + fifo.sink.valid.eq(dbus.store | dbus.load), + fifo.sink.we.eq(dbus.store), + fifo.sink.addr.eq(dbus.addr), + fifo.sink.data.eq(dbus.data_s), + fifo.sink.sel.eq(dbus.sel), + ] + + self.fsm = fsm = FSM(reset_state="IDLE") + fsm.act("IDLE", + If(fifo.source.valid, + If(fifo.source.we, + NextState("WRITE") + ).Else( + NextState("READ") + ) + ) + ) + fsm.act("WRITE", + wb_dbus.stb.eq(1), + wb_dbus.cyc.eq(1), + wb_dbus.we.eq(1), + wb_dbus.adr.eq(fifo.source.addr), + wb_dbus.sel.eq(fifo.source.sel), + wb_dbus.dat_w.eq(fifo.source.data), + If(wb_dbus.ack, + fifo.source.ready.eq(1), + dbus.store_done.eq(1), + NextState("IDLE") + ) + ) + fsm.act("READ", + wb_dbus.stb.eq(1), + wb_dbus.cyc.eq(1), + wb_dbus.we.eq(0), + wb_dbus.adr.eq(fifo.source.addr), + wb_dbus.sel.eq(fifo.source.sel), + If(wb_dbus.ack, + fifo.source.ready.eq(1), + dbus.load_done.eq(1), + dbus.data_l.eq(wb_dbus.dat_r), + NextState("IDLE") + ) + ) + # uRV ---------------------------------------------------------------------------------------------- class uRV(CPU): @@ -97,18 +161,10 @@ class uRV(CPU): self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). - # uRV Signals. - # ------------ + # uRV Buses. + # ---------- im_bus = Record(instruction_bus_layout) - - dm_addr = Signal(32) - dm_data_s = Signal(32) - dm_data_l = Signal(32) - dm_data_select = Signal(4) - dm_store = Signal() - dm_load = Signal() - dm_load_done = Signal() - dm_store_done = Signal() + dm_bus = Record(data_bus_layout) # uRV Instance. # ------------- @@ -134,70 +190,21 @@ class uRV(CPU): i_im_valid_i = im_bus.valid, # Data Mem Bus. - o_dm_addr_o = dm_addr, - o_dm_data_s_o = dm_data_s, - i_dm_data_l_i = dm_data_l, - o_dm_data_select_o = dm_data_select, + o_dm_addr_o = dm_bus.addr, + o_dm_data_s_o = dm_bus.data_s, + i_dm_data_l_i = dm_bus.data_l, + o_dm_data_select_o = dm_bus.sel, - o_dm_store_o = dm_store, - o_dm_load_o = dm_load, - i_dm_load_done_i = dm_load_done, - i_dm_store_done_i = dm_store_done, + o_dm_store_o = dm_bus.store, + o_dm_load_o = dm_bus.load, + i_dm_load_done_i = dm_bus.load_done, + i_dm_store_done_i = dm_bus.store_done, ) # uRV Bus Adaptation. # ------------------- self.submodules += InstructionBusToWishbone(im_bus, ibus) - - # uRV Data Bus. - # ------------- - self.dm_fifo = dm_fifo = stream.SyncFIFO( - layout = [("addr", 32), ("we", 1), ("data", 32), ("sel", 4)], - depth = 16, - ) - self.comb += [ - dm_fifo.sink.valid.eq(dm_store | dm_load), - dm_fifo.sink.we.eq(dm_store), - dm_fifo.sink.addr.eq(dm_addr), - dm_fifo.sink.data.eq(dm_data_s), - dm_fifo.sink.sel.eq(dm_data_select), - ] - self.dm_fsm = dm_fsm = FSM(reset_state="IDLE") - dm_fsm.act("IDLE", - If(dm_fifo.source.valid, - If(dm_fifo.source.we, - NextState("WRITE") - ).Else( - NextState("READ") - ) - ) - ) - dm_fsm.act("WRITE", - dbus.stb.eq(1), - dbus.cyc.eq(1), - dbus.we.eq(1), - dbus.adr.eq(dm_fifo.source.addr), - dbus.sel.eq(dm_fifo.source.sel), - dbus.dat_w.eq(dm_fifo.source.data), - If(dbus.ack, - dm_fifo.source.ready.eq(1), - dm_store_done.eq(1), - NextState("IDLE") - ) - ) - dm_fsm.act("READ", - dbus.stb.eq(1), - dbus.cyc.eq(1), - dbus.we.eq(0), - dbus.adr.eq(dm_fifo.source.addr), - dbus.sel.eq(dm_fifo.source.sel), - If(dbus.ack, - dm_fifo.source.ready.eq(1), - dm_load_done.eq(1), - dm_data_l.eq(dbus.dat_r), - NextState("IDLE") - ) - ) + self.submodules += DataBusToWishbone(dm_bus, dbus) # Add Verilog sources. # --------------------