From 9f91348c1ca3589bba6dee7b2c0c3f49ad9c72e5 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 10 Feb 2015 11:22:23 +0100
Subject: [PATCH] udp/crossbar: add possibility to get port with dw != 8 (16,
 32, 64, ...)

---
 liteeth/core/ip/crossbar.py  |  2 +-
 liteeth/core/udp/crossbar.py | 24 ++++++++++++++++++++----
 liteeth/test/udp_tb.py       | 17 ++++++++++-------
 3 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/liteeth/core/ip/crossbar.py b/liteeth/core/ip/crossbar.py
index b008130d8..edff815b1 100644
--- a/liteeth/core/ip/crossbar.py
+++ b/liteeth/core/ip/crossbar.py
@@ -11,9 +11,9 @@ class LiteEthIPV4Crossbar(Module):
 		self.master = LiteEthIPV4MasterPort(8)
 
 	def get_port(self, protocol):
-		port = LiteEthIPV4UserPort(8)
 		if protocol in self.users.keys():
 			raise ValueError("Protocol {0:#x} already assigned".format(protocol))
+		port = LiteEthIPV4UserPort(8)
 		self.users[protocol] = port
 		return port
 
diff --git a/liteeth/core/udp/crossbar.py b/liteeth/core/udp/crossbar.py
index f533a6775..ccc7594d6 100644
--- a/liteeth/core/udp/crossbar.py
+++ b/liteeth/core/udp/crossbar.py
@@ -10,12 +10,28 @@ class LiteEthUDPCrossbar(Module):
 		self.users = OrderedDict()
 		self.master = LiteEthUDPMasterPort(8)
 
-	def get_port(self, udp_port):
-		port = LiteEthUDPUserPort(8)
+	def get_port(self, udp_port, dw=8):
 		if udp_port in self.users.keys():
 			raise ValueError("Port {0:#x} already assigned".format(udp_port))
-		self.users[udp_port] = port
-		return port
+		user_port = LiteEthUDPUserPort(dw)
+		internal_port = LiteEthUDPUserPort(8)
+		if dw != 8:
+			converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
+			self.submodules += converter
+			self.comb += [
+				Record.connect(user_port.sink, converter.sink),
+				Record.connect(converter.source, internal_port.sink)
+			]
+			converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
+			self.submodules += converter
+			self.comb += [
+				Record.connect(internal_port.source, converter.sink),
+				Record.connect(converter.source, user_port.source)
+			]
+			self.users[udp_port] = internal_port
+		else:
+			self.users[udp_port] = user_port
+		return user_port
 
 	def do_finalize(self):
 		# TX arbitrate
diff --git a/liteeth/test/udp_tb.py b/liteeth/test/udp_tb.py
index b0274773c..74811dc7b 100644
--- a/liteeth/test/udp_tb.py
+++ b/liteeth/test/udp_tb.py
@@ -13,7 +13,8 @@ ip_address = 0x12345678
 mac_address = 0x12345678abcd
 
 class TB(Module):
-	def __init__(self):
+	def __init__(self, dw=8):
+		self.dw = dw
 		self.submodules.phy_model = phy.PHY(8, debug=False)
 		self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
 		self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
@@ -21,15 +22,15 @@ class TB(Module):
 		self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=True)
 
 		self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
-		udp_port = self.core.udp.crossbar.get_port(0x5678)
-		self.submodules.streamer = PacketStreamer(eth_udp_user_description(8))
-		self.submodules.logger = PacketLogger(eth_udp_user_description(8))
+		udp_port = self.core.udp.crossbar.get_port(0x5678, dw)
+		self.submodules.streamer = PacketStreamer(eth_udp_user_description(dw))
+		self.submodules.logger = PacketLogger(eth_udp_user_description(dw))
 		self.comb += [
 			Record.connect(self.streamer.source, udp_port.sink),
 			udp_port.sink.ip_address.eq(0x12345678),
 			udp_port.sink.src_port.eq(0x1234),
 			udp_port.sink.dst_port.eq(0x5678),
-			udp_port.sink.length.eq(64),
+			udp_port.sink.length.eq(64//(dw//8)),
 			Record.connect(udp_port.source, self.logger.sink)
 		]
 
@@ -54,7 +55,7 @@ class TB(Module):
 			yield
 
 		while True:
-			packet = Packet([i for i in range(64)])
+			packet = Packet([i for i in range(64//(self.dw//8))])
 			yield from self.streamer.send(packet)
 			yield from self.logger.receive()
 
@@ -64,4 +65,6 @@ class TB(Module):
 
 
 if __name__ == "__main__":
-	run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+	run_simulation(TB(8), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+	run_simulation(TB(16), ncycles=2048, vcd_name="my.vcd", keep_files=True)
+	run_simulation(TB(32), ncycles=2048, vcd_name="my.vcd", keep_files=True)
\ No newline at end of file