From 9fa1b4c123ab4d761e576ad3ec51c8b6658f5925 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 12 Jul 2024 16:17:30 +0200 Subject: [PATCH] Update Nax/Vexii --- litex/soc/cores/cpu/naxriscv/core.py | 3 +-- litex/soc/cores/cpu/vexiiriscv/core.py | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 0315cb827..e362fbf0a 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -320,9 +320,8 @@ class NaxRiscv(CPU): def generate_netlist(reset_address): vdir = get_data_mod("cpu", "naxriscv").data_location ndir = os.path.join(vdir, "ext", "NaxRiscv") - sdir = os.path.join(vdir, "ext", "SpinalHDL") - NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "43195dd1", NaxRiscv.update_repo) + NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "ba63ee6d", NaxRiscv.update_repo) gen_args = [] gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}") diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index d63c83637..c15c2dc83 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -156,7 +156,7 @@ class VexiiRiscv(CPU): VexiiRiscv.vexii_args += " --with-mul --with-div --allow-bypass-from=0 --performance-counters=0" VexiiRiscv.vexii_args += " --fetch-l1 --fetch-l1-ways=2" VexiiRiscv.vexii_args += " --lsu-l1 --lsu-l1-ways=2 --with-lsu-bypass" - VexiiRiscv.vexii_args += " --relaxed-branch --relaxed-btb" + VexiiRiscv.vexii_args += " --relaxed-branch" if args.cpu_variant in ["linux", "debian"]: VexiiRiscv.vexii_args += " --with-rva --with-supervisor" @@ -164,7 +164,7 @@ class VexiiRiscv(CPU): VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64" if args.cpu_variant in ["debian"]: - VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy" + VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy --fpu-ignore-subnormal" if args.cpu_variant in ["linux", "debian"]: VexiiRiscv.vexii_args += " --with-btb --with-ras --with-gshare"