From a048ba47c4db99b54fcee7bf994422c1d9308d9e Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 4 May 2019 17:27:21 +0100 Subject: [PATCH] vexriscv: Fix some floating signals Signed-off-by: David Shah --- litex/soc/cores/cpu/vexriscv/core.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index e40a2d38e..de30de8d5 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -126,6 +126,9 @@ class VexRiscv(Module, AutoCSR): i_dBusWishbone_ERR=dbus.err) if "linux" in variant: + # Tie zero to prevent 1'bx here + self.cpu_params["i_softwareInterrupt"] = 0 + self.cpu_params["i_externalInterruptS"] = 0 self.add_timer() if "debug" in variant: