From a071cc343db0686799faf8df0e281c3d67d052dd Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 31 Aug 2023 11:36:24 +0200 Subject: [PATCH] litex/soc/integration/soc: add_etherxx: when eth_rx_clk is eth_tx_clk only apply constraints on eth_rx_clk --- litex/soc/integration/soc.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index b46bfb68f..558a674eb 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1702,8 +1702,11 @@ class LiteXSoC(SoC): eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False): self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) - self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) - self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) + if not eth_rx_clk is eth_tx_clk: + self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) + else: + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk) # Add Etherbone -------------------------------------------------------------------------------- def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8, @@ -1761,8 +1764,11 @@ class LiteXSoC(SoC): eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False): self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) - self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) - self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) + if not eth_rx_clk is eth_tx_clk: + self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) + else: + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk) # Add SPI Flash -------------------------------------------------------------------------------- def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", software_debug=False, **kwargs):