From a0df5baa552387b4533066ee8a8498d25463708c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Jun 2014 11:09:59 +0200 Subject: [PATCH] host: add support for various csr_data width (8 & 32 tested, but should work with others) --- miscope/host/regs.py | 11 ++++++----- miscope/host/uart2wishbone.py | 4 ++-- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/miscope/host/regs.py b/miscope/host/regs.py index 3b5cdb3b8..0eaef4443 100644 --- a/miscope/host/regs.py +++ b/miscope/host/regs.py @@ -1,11 +1,12 @@ import csv class MappedReg: - def __init__(self, readfn, writefn, name, addr, length, mode): + def __init__(self, readfn, writefn, name, addr, length, busword, mode): self.readfn = readfn self.writefn = writefn self.addr = addr self.length = length + self.busword = busword self.mode = mode def read(self): @@ -15,14 +16,14 @@ class MappedReg: for i in range(self.length): r |= self.readfn(self.addr + 4*i) if i != (self.length-1): - r <<= 8 + r <<= self.busword return r def write(self, value): if self.mode not in ["rw", "wo"]: raise KeyError(name + "register not writable") for i in range(self.length): - dat = (value >> ((self.length-1-i)*8)) & 0xff + dat = (value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1) self.writefn(self.addr + 4*i, dat) class MappedRegs: @@ -37,12 +38,12 @@ class MappedRegs: raise KeyError("No such register " + attr) -def build_map(addrmap, readfn, writefn): +def build_map(addrmap, busword, readfn, writefn): csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#') d = {} for item in csv_reader: name, addr, length, mode = item addr = int(addr.replace("0x", ""), 16) length = int(length) - d[name] = MappedReg(readfn, writefn, name, addr, length, mode) + d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode) return MappedRegs(d) \ No newline at end of file diff --git a/miscope/host/uart2wishbone.py b/miscope/host/uart2wishbone.py index ebed06149..01fa0103e 100644 --- a/miscope/host/uart2wishbone.py +++ b/miscope/host/uart2wishbone.py @@ -10,12 +10,12 @@ def write_b(uart, data): class Uart2Wishbone: WRITE_CMD = 0x01 READ_CMD = 0x02 - def __init__(self, port, baudrate=115200, addrmap=None, debug=False): + def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False): self.port = port self.baudrate = str(baudrate) self.debug = debug self.uart = serial.Serial(port, baudrate, timeout=0.25) - self.regs = build_map(addrmap, self.read, self.write) + self.regs = build_map(addrmap, busword, self.read, self.write) def open(self): self.uart.flushOutput()