From a1043d11c0ae1f038acb31b873073d5a73a21dc3 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 16 Jan 2012 19:38:39 +0100
Subject: [PATCH] examples/corelogic_conv: use two dividers

---
 examples/corelogic_conv.py | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/examples/corelogic_conv.py b/examples/corelogic_conv.py
index 4bf058ff2..dd9c986b7 100644
--- a/examples/corelogic_conv.py
+++ b/examples/corelogic_conv.py
@@ -1,8 +1,10 @@
 from migen.fhdl import verilog
-from migen.corelogic import roundrobin, divider
+from migen.corelogic import divider
 
-r = roundrobin.Inst(5)
-d = divider.Inst(16)
-frag = r.get_fragment() + d.get_fragment()
-o = verilog.convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
+d1 = divider.Inst(16)
+d2 = divider.Inst(16)
+frag = d1.get_fragment() + d2.get_fragment()
+o = verilog.convert(frag, {
+	d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
+	d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i})
 print(o)