From a1a57fd9623ed9ddeab2d8e4595e87155f50f2d5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 19 May 2014 11:27:08 +0200 Subject: [PATCH] mibuild: expose add_period_constraint (easier to use for simple designs than vendor specific code) --- mibuild/altera_quartus.py | 10 +++++----- mibuild/xilinx_ise.py | 14 +++++++------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 3571aa3ee..24d0e8c2c 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -8,14 +8,10 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG from mibuild import tools -def _add_period_constraint(platform, clk, period): - platform.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk) - platform.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk) - class CRG_SE(SimpleCRG): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - _add_period_constraint(platform, self.cd_sys.clk, period) + platform.add_period_constraint(platform, self.cd_sys.clk, period) def _format_constraint(c): if isinstance(c, Pins): @@ -99,3 +95,7 @@ class AlteraQuartusPlatform(GenericPlatform): _run_quartus(build_name, quartus_path) os.chdir("..") + + def add_period_constraint(self, clk, period): + self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk) + self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 25357ac41..2789358db 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -10,22 +10,17 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG from mibuild import tools -def _add_period_constraint(platform, clk, period): - if period is not None: - platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk"; -TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) - class CRG_SE(SimpleCRG): def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - _add_period_constraint(platform, self._clk, period) + platform.add_period_constraint(platform, self._clk, period) class CRG_DS(Module): def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): reset_less = rst_name is None self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less) self._clk = platform.request(clk_name) - _add_period_constraint(platform, self._clk.p, period) + platform.add_period_constraint(platform, self._clk.p, period) self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p), Instance.Input("IB", self._clk.n), @@ -245,3 +240,8 @@ class XilinxISEPlatform(GenericPlatform): self.map_opt, self.par_opt) os.chdir("..") + + def add_period_constraint(self, clk, period): + if period is not None: + self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}"; +TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk)