From a1e7aab35c621d6b151bb9b5a51593742ad6cae1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 4 Mar 2021 14:42:50 +0100 Subject: [PATCH] cores/clock/xilinx_usp/USPIDELAYCTRL: Apply USIDELAYCTRL's changes. --- litex/soc/cores/clock/xilinx_usp.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/xilinx_usp.py b/litex/soc/cores/clock/xilinx_usp.py index de4afb49b..7343bdee9 100644 --- a/litex/soc/cores/clock/xilinx_usp.py +++ b/litex/soc/cores/clock/xilinx_usp.py @@ -93,7 +93,6 @@ class USPMMCM(XilinxClocking): class USPIDELAYCTRL(Module): def __init__(self, cd_ref, cd_sys, reset_cycles=64, ready_cycles=64): - cd_sys.rst.reset = 1 self.clock_domains.cd_ic = ClockDomain() ic_reset_counter = Signal(max=reset_cycles, reset=reset_cycles-1) ic_reset = Signal(reset=1) @@ -109,6 +108,7 @@ class USPIDELAYCTRL(Module): ic_ready = Signal() self.comb += self.cd_ic.clk.eq(cd_sys.clk) self.sync.ic += [ + cd_sys.rst.eq(1), If(ic_ready, If(ic_ready_counter != 0, ic_ready_counter.eq(ic_ready_counter - 1)