diff --git a/litex/soc/cores/cpu/naxriscv/RamXilinx.v b/litex/soc/cores/cpu/naxriscv/RamXilinx.v deleted file mode 100644 index c6e6a967e..000000000 --- a/litex/soc/cores/cpu/naxriscv/RamXilinx.v +++ /dev/null @@ -1,46 +0,0 @@ - -module Ram_1w_1rs #( - parameter integer wordCount = 0, - parameter integer wordWidth = 0, - parameter clockCrossing = 1'b0, - parameter technology = "auto", - parameter readUnderWrite = "dontCare", - parameter integer wrAddressWidth = 0, - parameter integer wrDataWidth = 0, - parameter integer wrMaskWidth = 0, - parameter wrMaskEnable = 1'b0, - parameter integer rdAddressWidth = 0, - parameter integer rdDataWidth = 0 - )( - input wr_clk, - input wr_en, - input [wrMaskWidth-1:0] wr_mask, - input [wrAddressWidth-1:0] wr_addr, - input [wrDataWidth-1:0] wr_data, - input rd_clk, - input rd_en, - input [rdAddressWidth-1:0] rd_addr, - output [rdDataWidth-1:0] rd_data - ); - - reg [wrDataWidth-1:0] ram_block [(2**wrAddressWidth)-1:0]; - integer i; - localparam COL_WIDTH = wrDataWidth/wrMaskWidth; - always @ (posedge wr_clk) begin - if(wr_en) begin - for(i=0;i # Copyright (c) 2020-2022 Dolu1990 # SPDX-License-Identifier: BSD-2-Clause - +import hashlib import os +import subprocess from os import path from migen import * +from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.interconnect import axi from litex.soc.interconnect.csr import * @@ -42,6 +44,9 @@ class NaxRiscv(CPU): # Default parameters. with_fpu = False with_rvc = False + scala_files = ["misc.scala", "fetch.scala", "frontend.scala", "branch_predictor_std.scala", "lsu.scala", "eu_2alu_1share.scala"] + netlist_name = None + scala_paths = [] # ABI. @staticmethod @@ -81,6 +86,20 @@ class NaxRiscv(CPU): flags += f" -DUART_POLLING" return flags + + # Command line configuration arguments. + @staticmethod + def args_fill(parser): + cpu_group = parser.add_argument_group("cpu") + cpu_group.add_argument("--scala-file", action='append', help="Specify the scala files used to configure NaxRiscv") + + @staticmethod + def args_read(args): + print(args) + if args.scala_file: + NaxRiscv.scala_files = args.scala_file + + def __init__(self, platform, variant): self.platform = platform self.variant = "standard" @@ -140,14 +159,90 @@ class NaxRiscv(CPU): self.reset_address = reset_address assert reset_address == 0x00000000 + @staticmethod + def find_scala_files(): + vdir = get_data_mod("cpu", "naxriscv").data_location + for file in NaxRiscv.scala_files: + if os.path.exists(file): + NaxRiscv.scala_paths.append(os.path.abspath(file)) + else: + path = os.path.join(vdir, "configs", file) + if os.path.exists(path): + NaxRiscv.scala_paths.append(path) + else: + raise Exception(f"Can't find NaxRiscv's {file}") + + # Cluster Name Generation. + @staticmethod + def generate_netlist_name(): + md5_hash = hashlib.md5() + for file in NaxRiscv.scala_paths: + a_file = open(file, "rb") + content = a_file.read() + md5_hash.update(content) + + digest = md5_hash.hexdigest() + NaxRiscv.netlist_name = "NaxRiscvLitex_" + digest + + + @staticmethod + def git_setup(name, dir, repo, hash): + if not os.path.exists(dir): + # Clone Repo. + print(f"Cloning {name} Git repository...") + subprocess.check_call("git clone {url} {options}".format( + url = repo, + options = dir + ), shell=True) + # Use specific SHA1 (Optional). + os.chdir(os.path.join(dir)) + os.system(f"cd {dir} && git checkout {hash}") + + # Netlist Generation. + @staticmethod + def generate_netlist(): + vdir = get_data_mod("cpu", "naxriscv").data_location + ndir = os.path.join(vdir, "ext", "NaxRiscv") + sdir = os.path.join(vdir, "ext", "SpinalHDL") + + # NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "c883e74e") + # NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "10cfe066") + + + gen_args = [] + gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}") + gen_args.append(f"--netlist-directory={vdir}") + for file in NaxRiscv.scala_paths: + gen_args.append(f"--scala-file={file}") + + cmd = f"""cd {ndir} && sbt "runMain naxriscv.platform.LitexGen {" ".join(gen_args)}\"""" + print("NaxRiscv generation command :") + print(cmd) + if os.system(cmd) != 0: + raise OSError('Failed to run sbt') + + def add_sources(self, platform): - cdir = os.path.abspath(os.path.dirname(__file__)) - # FIXME: Create pythondata-cpu-naxriscv once working. - if not os.path.exists(f"{cdir}/NaxRiscvLitex.v"): - os.system(f"wget https://github.com/enjoy-digital/litex_naxriscv_test/files/8059827/NaxRiscvLitex.v.txt -P {cdir}") - os.system(f"mv {cdir}/NaxRiscvLitex.v.txt {cdir}/NaxRiscvLitex.v") - platform.add_source(os.path.join(cdir, "NaxRiscvLitex.v")) - platform.add_source(os.path.join(cdir, "RamXilinx.v")) + vdir = get_data_mod("cpu", "naxriscv").data_location + print(f"NaxRiscv netlist : {self.netlist_name}") + if not path.exists(os.path.join(vdir, self.netlist_name + ".v")): + self.generate_netlist() + + # Add RAM. + # By default, use Generic RAM implementation. + ram_filename = "Ram_1w_1rs_Generic.v" + # On Altera/Intel platforms, use specific implementation. + from litex.build.altera import AlteraPlatform + if isinstance(platform, AlteraPlatform): + ram_filename = "Ram_1w_1rs_Intel.v" + # On Efinix platforms, use specific implementation. + from litex.build.efinix import EfinixPlatform + if isinstance(platform, EfinixPlatform): + ram_filename = "Ram_1w_1rs_Efinix.v" + platform.add_source(os.path.join(vdir, ram_filename), "verilog") + + # Add Cluster. + platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog") def add_soc_components(self, soc, soc_region_cls): soc.csr.add("uart", n=2) @@ -272,8 +367,13 @@ class NaxRiscv(CPU): def do_finalize(self): assert hasattr(self, "reset_address") + + self.find_scala_files() + self.generate_netlist_name() + # Do verilog instance. - self.specials += Instance("NaxRiscvLitex", **self.cpu_params) + self.specials += Instance(self.netlist_name, **self.cpu_params) + # Add verilog sources self.add_sources(self.platform) diff --git a/litex_setup.py b/litex_setup.py index e55e44de0..100f1a934 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -99,6 +99,7 @@ git_repos = { "pythondata-cpu-serv": GitRepo(url="https://github.com/litex-hub/"), "pythondata-cpu-vexriscv": GitRepo(url="https://github.com/litex-hub/"), "pythondata-cpu-vexriscv-smp": GitRepo(url="https://github.com/litex-hub/", clone="recursive"), + "pythondata-cpu-naxriscv": GitRepo(url="https://github.com/litex-hub/"), "pythondata-cpu-rocket": GitRepo(url="https://github.com/litex-hub/"), "pythondata-cpu-minerva": GitRepo(url="https://github.com/litex-hub/"), "pythondata-cpu-microwatt": GitRepo(url="https://github.com/litex-hub/", sha1=0xb940b55acff),